Vijaylakshmi Srinivasan
Vijaylakshmi Srinivasan
IBM T.J. Watson Research Center
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TitleCited byYear
Scalable high performance main memory system using phase-change memory technology
MK Qureshi, V Srinivasan, JA Rivers
ACM SIGARCH Computer Architecture News 37 (3), 24-33, 2009
Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling
MK Qureshi, J Karidis, M Franceschini, V Srinivasan, L Lastras, B Abali
Proceedings of the 42nd annual IEEE/ACM international symposium on …, 2009
NDC: Analyzing the impact of 3D-stacked memory+ logic devices on MapReduce workloads
SH Pugsley, J Jestes, H Zhang, R Balasubramonian, V Srinivasan, ...
2014 IEEE International Symposium on Performance Analysis of Systems and …, 2014
SAFER: Stuck-at-fault error recovery for memories
NH Seong, DH Woo, V Srinivasan, JA Rivers, HHS Lee
Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on …, 2010
A tagless coherence directory
J Zebchuk, V Srinivasan, MK Qureshi, A Moshovos
Proceedings of the 42nd Annual IEEE/ACM International Symposium on …, 2009
Branch history guided instruction/data prefetching
TR Puzak, AM Hartstein, M Charney, DA Prener, PH Oden, V Srinivasan
US Patent 6,560,693, 2003
Method and apparatus for prefetching branch history information
PG Emma, KJ Getzlaff, AM Hartstein, T Pflueger, TR Puzak, EM Schwarz, ...
US Patent 7,493,480, 2009
Integrated analysis of power and performance for pipelined microprocessors
V Zyuban, D Brooks, V Srinivasan, M Gschwind, P Bose, PN Strenski, ...
IEEE Transactions on Computers 53 (8), 1004-1016, 2004
Programming with relaxed synchronization
L Renganarayana, V Srinivasan, R Nair, D Prener
Proceedings of the 2012 ACM workshop on Relaxing synchronization for …, 2012
Iterative write pausing techniques to improve read latency of memory systems
MM Franceschini, LA Lastras-Montano, MK Qureshi, V Srinivasan
US Patent 8,004,884, 2011
Pact: Parameterized clipping activation for quantized neural networks
J Choi, Z Wang, S Venkataramani, PIJ Chuang, V Srinivasan, ...
arXiv preprint arXiv:1805.06085, 2018
Spatl: Honey, i shrunk the coherence directory
H Zhao, A Shriraman, S Dwarkadas, V Srinivasan
2011 International Conference on Parallel Architectures and Compilation …, 2011
On the nature of cache miss behavior: Is it√ 2
A Hartstein, V Srinivasan, T Puzak, P Emma
The Journal of Instruction-Level Parallelism 10, 1-22, 2008
Comparing implementations of near-data computing with in-memory mapreduce workloads
SH Pugsley, J Jestes, R Balasubramonian, V Srinivasan, ...
IEEE Micro 34 (4), 44-52, 2014
Processor with low overhead predictive supply voltage gating for leakage power reduction
P Bose, DM Brooks, PW Cook, PG Emma, MK Gschwind, SE Schuster, ...
US Patent 7,134,028, 2006
Co-designing accelerators and soc interfaces using gem5-aladdin
YS Shao, SL Xi, V Srinivasan, GY Wei, D Brooks
2016 49th Annual IEEE/ACM International Symposium on Microarchitecture …, 2016
Predicting cache misses using data access behavior and instruction address
V Srinivasan, BR Prasky
US Patent 10,007,523, 2018
Active management of data caches by exploiting reuse information
ES Tam, JA Rivers, V Srinivasan, GS Tyson, ES Davidson
IEEE Transactions on Computers 48 (11), 1244-1259, 1999
Approximate computing: Challenges and opportunities
A Agrawal, J Choi, K Gopalakrishnan, S Gupta, R Nair, J Oh, DA Prener, ...
2016 IEEE International Conference on Rebooting Computing (ICRC), 1-8, 2016
Method and apparatus for an efficient multi-path trace cache design
GA Rasche, JA Rivers, V Srinivasan
US Patent 7,366,875, 2008
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