| CMOS-MEMS accelerometer with stepped suspended gate FET array: Design & analysis P Martha, N Kadayinti, V Seena IEEE Transactions on Electron Devices 68 (10), 5133-5141, 2021 | 6 | 2021 |
| A feed-forward equalizer for capacitively coupled on-chip interconnect K Naveen, M Dave, MS Baghini, DK Sharma 2013 26th International Conference on VLSI Design and 2013 12th …, 2013 | 6 | 2013 |
| A CMOS-MEMS accelerometer with u-channel suspended gate SOI FET P Martha, N Kadayinti, V Seena IEEE Sensors Journal 21 (9), 10465-10472, 2021 | 5 | 2021 |
| Sense amplifier comparator with offset correction for decision feedback equalization based receivers N Kadayinti, DK Sharma Microelectronics journal 70, 27-33, 2017 | 5 | 2017 |
| A clock synchronizer for repeaterless low swing on-chip links N Kadayinti, MS Baghini, DK Sharma arXiv preprint arXiv:1510.04241, 2015 | 5 | 2015 |
| A technique for modeling and simulating transistor based MEMS sensors P Martha, A Sebastian, V Seena, N Kadayinti 2021 IEEE International Symposium on Inertial Sensors and Systems (INERTIAL …, 2021 | 3 | 2021 |
| Effect of jitter on the settling time of mesochronous clock retiming circuits N Kadayinti, AJ Budkuley, MS Baghini, DK Sharma Analog Integrated Circuits and Signal Processing 101, 623-640, 2019 | 3 | 2019 |
| A clock retiming circuit for repeaterless low swing on-chip interconnects N Kadayinti, MS Baghini, DK Sharma 2017 30th International Conference on VLSI Design and 2017 16th …, 2017 | 3 | 2017 |
| Testable design of repeaterless low swing on-chip interconnect K Naveen, DK Sharma 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 563-566, 2016 | 3 | 2016 |
| Settling time of mesochronous clock re-timing circuits in the presence of timing jitter N Kadayinti, AJ Budkuley, DK Sharma 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 2 | 2017 |
| Frequency Range Enhancement in Differential Ring VCO while Maintaining Phase Noise Performance MK SINGH, P Singh, N Kadayinti, D Das, M Sakare Authorea Preprints, 2023 | 1 | 2023 |
| A Closed-Loop In-Plane Movable Suspended Gate FET (CLIP-SGFET) Sensor With a Dynamically Reconfigurable Charge Pump P Martha, KM Ganga, A Sebastian, V Seena, N Kadayinti IEEE Sensors Journal 22 (22), 21550-21560, 2022 | 1 | 2022 |
| Testable Design of Repeaterless Low Swing On-Chip Interconnect N Kadayinti, DK Sharma arXiv preprint arXiv:1511.06726, 2015 | 1 | 2015 |
| Mismatch Tolerant Negative Conductance Load Tuning for High Gain OTAs MS Marinaik, N Kadayinti 2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 363-366, 2023 | | 2023 |
| CMOS-MEMS Nano Force Sensor with Sub-μm U-Channel Suspended Gate SOIFET P Martha, N Kadayinti, V Seena 2023 IEEE Applied Sensing Conference (APSCON), 1-3, 2023 | | 2023 |
| A True Time Delay Element using Cascaded Variable Bandwidth All Pass Filters MS Marinaik, GK Maheshwarappa, N Kadayinti 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 3473-3477, 2022 | | 2022 |
| Impact of Sampler Offset on Jitter Transfer in Clock and Data Recovery Circuits N Kadayinti, MS Baghini, DK Sharma arXiv preprint arXiv:2001.03553, 2020 | | 2020 |
| Measurements of the effect of jitter on the performance of clock retiming circuits for on-chip interconnects N Kadayinti, MS Baghini, DK Sharma Microelectronics Journal 81, 101-106, 2018 | | 2018 |
| Clock Skew Measurement Using an All-Digital Sigma-Delta Time to Digital Converter MG Shirwaikar, N Kadayinti, DK Sharma 2017 30th International Conference on VLSI Design and 2017 16th …, 2017 | | 2017 |
| Settling Time of Mesochronous Clock Retiming Circuits for Low Swing Interconnects. N Kadayinti, AJ Budkuley, DK Sharma arXiv preprint arXiv:1604.00230, 2016 | | 2016 |
Maryam Shojaei BaghiniProfessor of Electrical Engineering, IIT-BombayDirección de correo verificada de iitb.ac.in
