| Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits PF Butzen, LS da Rosa Jr, EJD Chiappetta Filho, AI Reis, RP Ribas Microelectronics Journal 41 (4), 247-255, 2010 | 31 | 2010 |
| Electronically programmable test points for on-chip analog/digital measurements M Franco, J Güiza, E Chiappetta, S Rueda, H Luis, J Bertuzzo, J Koeppe, ... 2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2670-2673, 2013 | 3 | 2013 |
| Subthreshold and gate leakage estimation in complex gates PF Butzen, LS Rosa Jr, EJD Chiappetta Filho, DS Moura, AI Reis, ... IEEE INTERNATIONAL WORKSHOP ON LOGIC AND SYNTHESIS, IWLS 17, 2008 | 3 | 2008 |
| Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms PF Butzen, LS Rosa Jr, EJD Chiappetta Filho, DS Moura, AI Reis, ... Proceedings of the 18th ACM Great Lakes symposium on VLSI, 407-410, 2008 | 2 | 2008 |
| Fully Automated, Low Cost, Bench-Testing Solution for Analog/Mixed-Signal Integrated Circuits E Chiappetta, S Rueda, M Franco, F Souza, J Güiza, J Bertuzzo, J Jenkins | | |
| A SIMPLE MODEL TO ESTIMATE INTRINSIC POWER CONSUMPTION IN CMOS LOGIC GATES EJD Chiappetta Filho, RP Ribas, PF Butzen, LS da Rosa Jr, AI Reis | | |
Paulo Francisco ButzenProfessor at Federal University of Rio Grande SulVerified email at ufrgs.br
