| PERCIVAL: Open-Source Posit RISC-V Core with Quire Capability D Mallasén, R Murillo, AA Del Barrio, G Botella, L Piñuel, M Prieto-Matias IEEE Transactions on Emerging Topics in Computing 10 (3), 1241-1252, 2022 | 28 | 2022 |
| Energy-Efficient MAC Units for Fused Posit Arithmetic R Murillo, D Mallasén, AA Del Barrio, G Botella 2021 IEEE 39th International Conference on Computer Design (ICCD), 138-145, 2021 | 15 | 2021 |
| Comparing different decodings for posit arithmetic R Murillo, D Mallasén, AA Del Barrio, G Botella Conference on Next Generation Arithmetic, 84-99, 2022 | 11 | 2022 |
| Customizing the CVA6 RISC-V Core to Integrate Posit and Quire Instructions D Mallasén, R Murillo, AA Del Barrio, G Botella, L Piñuel, M Prieto–Matias 2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS), 01-06, 2022 | 3 | 2022 |
| LiveChess2FEN: a Framework for Classifying Chess Pieces based on CNNs D Mallasén Quintana, AA del Barrio García, M Prieto Matías arXiv preprint arXiv:2012.06858, 2020 | 3 | 2020 |
| PLAUs: Posit Logarithmic Approximate Units to Implement Low-Cost Operations with Real Numbers R Murillo, D Mallasén, AA Del Barrio, G Botella Next Generation Arithmetic: 4th International Conference, CoNGA 2023 …, 2023 | 1 | 2023 |
| Big-PERCIVAL: Exploring the Native Use of 64-Bit Posit Arithmetic in Scientific Computing D Mallasén, AA Del Barrio, M Prieto-Matias arXiv preprint arXiv:2305.06946, 2023 | 1 | 2023 |
| Leveraging Posits for the Conjugate Gradient Linear Solver on an Application-Level RISC-V Core D Mallasén Quintana | | 2022 |
| Técnicas de aceleración para el reconocimiento de piezas de ajedrez D Mallasén Quintana Universidad Complutense de Madrid, 2020 | | 2020 |
Alberto A. del BarrioIEEE/ACM Senior Member, Associate Professor (tenured, civil-servant) of Computer ScienceVerified email at ucm.es
