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David Mallasén Quintana
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PERCIVAL: Open-Source Posit RISC-V Core with Quire Capability
D Mallasén, R Murillo, AA Del Barrio, G Botella, L Piñuel, M Prieto-Matias
IEEE Transactions on Emerging Topics in Computing 10 (3), 1241-1252, 2022
9*2022
Energy-Efficient MAC Units for Fused Posit Arithmetic
R Murillo, D Mallasén, AA Del Barrio, G Botella
2021 IEEE 39th International Conference on Computer Design (ICCD), 138-145, 2021
82021
Comparing different decodings for posit arithmetic
R Murillo, D Mallasén, AA Del Barrio, G Botella
Next Generation Arithmetic: Third International Conference, CoNGA 2022 …, 2022
42022
LiveChess2FEN: a Framework for Classifying Chess Pieces based on CNNs
D Mallasén Quintana, AA del Barrio García, M Prieto Matías
arXiv preprint arXiv:2012.06858, 2020
12020
Customizing the CVA6 RISC-V Core to Integrate Posit and Quire Instructions
D Mallasén, R Murillo, AA Del Barrio, G Botella, L Piñuel, M Prieto–Matias
2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS), 01-06, 2022
2022
Leveraging Posits for the Conjugate Gradient Linear Solver on an Application-Level RISC-V Core
D Mallasén Quintana
2022
Técnicas de aceleración para el reconocimiento de piezas de ajedrez
D Mallasén Quintana
Universidad Complutense de Madrid, 2020
2020
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