| A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3 ns and 55.8 TOPS/W fully parallel product-sum operation for binary DNN edge processors WS Khwa, JJ Chen, JF Li, X Si, EY Yang, X Sun, R Liu, PY Chen, Q Li, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 496-498, 2018 | 250 | 2018 |
| DNN+ NeuroSim: An end-to-end benchmarking framework for compute-in-memory accelerators with versatile device technologies X Peng, S Huang, Y Luo, X Sun, S Yu 2019 IEEE international electron devices meeting (IEDM), 32.5. 1-32.5. 4, 2019 | 248 | 2019 |
| XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks X Sun, S Yin, X Peng, R Liu, J Seo, S Yu 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018 | 235 | 2018 |
| 24.5 A twin-8T SRAM computation-in-memory macro for multiple-bit CNN-based machine learning X Si, JJ Chen, YN Tu, WH Huang, JH Wang, YC Chiu, WC Wei, SY Wu, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 396-398, 2019 | 227 | 2019 |
| A twin-8T SRAM computation-in-memory unit-macro for multibit CNN-based AI edge processors X Si, JJ Chen, YN Tu, WH Huang, JH Wang, YC Chiu, WC Wei, SY Wu, ... IEEE Journal of Solid-State Circuits 55 (1), 189-202, 2019 | 156 | 2019 |
| A dual-split 6T SRAM-based computing-in-memory unit-macro with fully parallel product-sum operation for binarized DNN edge processors X Si, WS Khwa, JJ Chen, JF Li, X Sun, R Liu, S Yu, H Yamauchi, Q Li, ... IEEE Transactions on Circuits and Systems I: Regular Papers 66 (11), 4172-4185, 2019 | 130 | 2019 |
| High-throughput in-memory computing for binary deep neural networks with monolithically integrated RRAM and 90-nm CMOS S Yin, X Sun, S Yu, J Seo IEEE Transactions on Electron Devices 67 (10), 4185-4192, 2020 | 125 | 2020 |
| Impact of non-ideal characteristics of resistive synaptic devices on implementing convolutional neural networks X Sun, S Yu IEEE Journal on Emerging and Selected Topics in Circuits and Systems 9 (3 …, 2019 | 121 | 2019 |
| Parallelizing SRAM arrays with customized bit-cell for binary neural networks R Liu, X Peng, X Sun, WS Khwa, X Si, JJ Chen, JF Li, MF Chang, S Yu Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 114 | 2018 |
| Fully parallel RRAM synaptic array for implementing binary neural network with (+1, −1) weights and (+1, 0) neurons X Sun, X Peng, PY Chen, R Liu, J Seo, S Yu Design Automation Conference (ASP-DAC), 2018 23rd Asia and South Pacific …, 2018 | 104 | 2018 |
| Exploiting hybrid precision for training and inference: A 2T-1FeFET based analog synaptic weight cell X Sun, P Wang, K Ni, S Datta, S Yu 2018 IEEE international electron devices meeting (IEDM), 3.1. 1-3.1. 4, 2018 | 103 | 2018 |
| Monolithically integrated RRAM-and CMOS-based in-memory computing optimizations for efficient deep learning S Yin, Y Kim, X Han, H Barnaby, S Yu, Y Luo, W He, X Sun, JJ Kim, J Seo IEEE Micro 39 (6), 54-63, 2019 | 81 | 2019 |
| 25.2 A Reconfigurable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source With <6×10−6 Native Bit Error Rate Y Pang, B Gao, D Wu, S Yi, Q Liu, WH Chen, TW Chang, WE Lin, X Sun, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 402-404, 2019 | 69 | 2019 |
| Compute-in-memory with emerging nonvolatile-memories: Challenges and prospects S Yu, X Sun, X Peng, S Huang 2020 ieee custom integrated circuits conference (cicc), 1-4, 2020 | 62 | 2020 |
| Characterizing endurance degradation of incremental switching in analog RRAM for neuromorphic systems M Zhao, H Wu, B Gao, X Sun, Y Liu, P Yao, Y Xi, X Li, Q Zhang, K Wang, ... 2018 IEEE International Electron Devices Meeting (IEDM), 20.2. 1-20.2. 4, 2018 | 62 | 2018 |
| 2-bit-per-cell RRAM-based in-memory computing for area-/energy-efficient deep learning W He, S Yin, Y Kim, X Sun, JJ Kim, S Yu, JS Seo IEEE Solid-State Circuits Letters 3, 194-197, 2020 | 48 | 2020 |
| A highly reliable RRAM physically unclonable function utilizing post-process randomness source B Lin, Y Pang, B Gao, J Tang, D Wu, TW Chang, WE Lin, X Sun, S Yu, ... IEEE Journal of Solid-State Circuits 56 (5), 1641-1650, 2021 | 35 | 2021 |
| Heterogeneous mixed-signal monolithic 3-D in-memory computing using resistive RAM G Murali, X Sun, S Yu, SK Lim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (2), 386-396, 2020 | 35 | 2020 |
| Computing-in-memory with SRAM and RRAM for binary neural networks X Sun, R Liu, X Peng, S Yu 2018 14th IEEE International Conference on Solid-State and Integrated …, 2018 | 34 | 2018 |
| Low-VDD operation of SRAM synaptic array for implementing ternary neural network X Sun, R Liu, YJ Chen, HY Chiu, WH Chen, MF Chang, S Yu IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (10 …, 2017 | 30 | 2017 |
Shimeng YuGeorgia Institute of Technology, Professor of ECEDirección de correo verificada de ece.gatech.edu
