Dr Simon J. Hollis
Dr Simon J. Hollis
Research Scientist at Facebook Reality Labs
Verified email at oculus.com - Homepage
Title
Cited by
Cited by
Year
A single ended 6T SRAM cell design for ultra-low-voltage applications
J Singh, DK Pradhan, S Hollis, SP Mohanty
IEICE Electronics Express 5 (18), 750-755, 2008
792008
A 6.7-ghz active gate driver for GaN FETs to combat overshoot, ringing, and EMI
HCP Dymond, J Wang, D Liu, JJO Dalton, N McNeill, D Pamunuwa, ...
IEEE Transactions on Power Electronics 33 (1), 581-594, 2018
552018
Identifying compiler options to minimize energy consumption for embedded platforms
J Pallister, SJ Hollis, J Bennett
The Computer Journal 58 (1), 95-109, 2013
542013
BEEBS: Open Benchmarks for Energy Measurements on Embedded Platforms
J Pallister, S Hollis, J Bennett
arXiv preprint arXiv:1308.5174, 2013
532013
Exploiting emergence in on-chip interconnects
SJ Hollis, C Jackson, P Bogdan, R Marculescu
IEEE Transactions on Computers 63 (3), 570-582, 2014
332014
Single ended 6T SRAM with isolated read-port for low-power embedded systems
J Singh, DK Pradhan, S Hollis, SP Mohanty, J Mathew
Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE'09 …, 2009
252009
Skip-links: A dynamically reconfiguring topology for energy-efficient NoCs
C Jackson, SJ Hollis
System on Chip (SoC), 2010 International Symposium on, 49-54, 2010
232010
Challenges for Energy Harvesting Systems Under Intermittent Excitation
G Yang, BH Stark, SJ Hollis, SG Burrow
IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), 2014
192014
A deadlock-free routing algorithm for dynamically reconfigurable Networks-on-Chip
C Jackson, SJ Hollis
Microprocessors and Microsystems 35 (2), 139-151, 2011
172011
RasP: an area-efficient, on-chip network
S Hollis, SW Moore
Computer Design, 2006. ICCD 2006. International Conference on, 63-69, 2007
162007
Shaping Switching Waveforms in a 650 V GaN FET Bridge-Leg Using 6.7 GHz Active Gate Drivers
BS J Dalton, J Wang, H Dymond, D Liu, D Pamunuwa, N McNeill, S Hollis
IEEE Applied Power Electronics Conference and Exposition 2017, 2017
14*2017
Design of 370 ps Delay Floating Voltage Level Shifters with 30 V/ns Power Supply Slew Tolerance
S Hollis, H Dymond, N McNeill, B Stark
IEEE Transactions on Circuits and Systems II [To appear], 2016
142016
Reduction of oscillations in a GaN bridge leg using active gate driving with sub-ns resolution, arbitrary gate-resistance patterns
HCP Dymond, D Liu, J Wang, JJO Dalton, N McNeill, D Pamunuwa, ...
Energy Conversion Congress and Exposition (ECCE), 2016 IEEE, 1-6, 2016
132016
A high-level model of embedded flash energy consumption
J Pallister, K Eder, SJ Hollis, J Bennett
Compilers, Architecture and Synthesis for Embedded Systems (CASES), 2014 …, 2014
132014
When does Network-on-Chip bypassing make sense?
SJ Hollis, C Jackson
SOC Conference, 2009. SOCC 2009. IEEE International, 143-146, 2009
132009
A new circuit topology for floating high voltage level shifters
D Liu, SJ Hollis, BH Stark
Microelectronics and Electronics (PRIME), 2014 10th Conference on Ph. D …, 2014
92014
Swallow: Building an Energy-Transparent Many-Core Embedded Real-Time System
SJ Hollis, S Kerrison
Design Automation and Test in Europe (DATE), 2016
82016
Optimizing the flash-RAM energy trade-off in deeply embedded systems
J Pallister, K Eder, SJ Hollis
Proceedings of the 13th Annual IEEE/ACM International Symposium on Code …, 2015
72015
Skip the Analysis: Self-Optimising Networks-on-Chip
SJ Hollis, C Jackson
Electronic System Design (ISED), 2010 International Symposium on, 14-19, 2010
62010
An area-efficient, pulse-based interconnect
S Hollis, SW Moore
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International …, 2006
62006
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Articles 1–20