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Sriram Aananthakrishnan
Sriram Aananthakrishnan
Verified email at intel.com
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Cited by
Year
A scalable and distributed dynamic formal verifier for MPI programs
A Vo, S Aananthakrishnan, G Gopalakrishnan, BR De Supinski, M Schulz, ...
SC'10: Proceedings of the 2010 ACM/IEEE International Conference for High …, 2010
1202010
PIUMA: programmable integrated unified memory architecture
S Aananthakrishnan, NK Ahmed, V Cave, M Cintra, Y Demir, KD Bois, ...
arXiv preprint arXiv:2010.06277, 2020
212020
Hybrid approach for data-flow analysis of MPI programs
S Aananthakrishnan, G Bronevetsky, G Gopalakrishnan
Proceedings of the 27th international ACM conference on International …, 2013
152013
Prune the unnecessary: Parallel pull-push louvain algorithms with automatic edge pruning
JJ Tithi, A Stasiak, S Aananthakrishnan, F Petrini
Proceedings of the 49th International Conference on Parallel Processing, 1-11, 2020
72020
Some resources for teaching concurrency
G Gopalakrishnan, Y Yang, S Vakkalanka, A Vo, S Aananthakrishnan, ...
Proceedings of the 7th Workshop on Parallel and Distributed Systems: Testing …, 2009
62009
Parfuse: Parallel and compositional analysis of message passing programs
S Aananthakrishnan, G Bronevetsky, M Baranowski, G Gopalakrishnan
Languages and Compilers for Parallel Computing: 29th International Workshop …, 2017
42017
How formal dynamic verification tools facilitate novel concurrency visualizations
S Aananthakrishnan, M DeLisi, S Vakkalanka, A Vo, G Gopalakrishnan, ...
European Parallel Virtual Machine/Message Passing Interface Users’ Group …, 2009
42009
Large-scale matrix restructuring and matrix-scalar operations
R Pawlowski, A More, V Cave, S Aananthakrishnan, JM Howard, ...
US Patent App. 17/134,251, 2022
32022
Compositional dataflow via abstract transition systems
G Bronevetsky, M Burke, S Aananthakrishnan, J Zhao, V Sarkar
Lawrence Livermore National Lab.(LLNL), Livermore, CA (United States), 2013
32013
Efficient sparse matrix-vector multiplication on intel piuma architecture
S Aananthakrishnan, R Pawlowski, J Fryman, I Hur
2020 IEEE High Performance Extreme Computing Conference (HPEC), 1-2, 2020
12020
Online and Real-time Object Tracking Algorithm with Extremely Small Matrices
JJ Tithi, S Aananthakrishnan, F Petrini
arXiv preprint arXiv:2003.12091, 2020
12020
Multi-dimensional network sorted array merging
R Pawlowski, S Aananthakrishnan
US Patent App. 18/131,143, 2024
2024
The Intel® Programmable and Integrated Unified Memory Architecture (PIUMA) Graph Analytics Processor
S Aananthakrishnan, S Abedin, V Cavé, F Checconi, K Du Bois, ...
IEEE Micro, 2023
2023
Memory system architecture for multi-threaded processors
R Pawlowski, A More, JM Howard, JB Fryman, TC Zhong, S Smith, ...
US Patent 11,630,691, 2023
2023
Cache support for indirect loads and indirect stores in graph applications
R Pawlowski, S Aananthakrishnan, J Howard, J Fryman
US Patent App. 17/359,305, 2022
2022
Memory system architecture for multi-threaded processors
R Pawlowski, A More, JM Howard, JB Fryman, TC Zhong, S Smith, ...
US Patent 11,106,494, 2021
2021
System, apparatus and method for barrier synchronization in a multi-threaded processor
R Pawlowski, A More, S Smith, S Pitchaimoorthy, S Jain, V Cavé, ...
US Patent 11,061,742, 2021
2021
Array broadcast and reduction systems and methods
J Fryman, A More, J Howard, R Pawlowski, Y Demir, N Pepperling, ...
US Patent 10,983,793, 2021
2021
Online and Real-time Object Tracking Algorithm with Extremely Small Matrices
J Jahan Tithi, S Aananthakrishnan, F Petrini
arXiv e-prints, arXiv: 2003.12091, 2020
2020
A composable static analysis framework for program analysis
S Aananthakrishnan
The University of Utah, 2016
2016
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Articles 1–20