Bernd Becker
Bernd Becker
Professor of Computer Science, University of Freiburg
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Cited by
Efficient representation and manipulation of switching functions based on ordered Kronecker functional decision diagrams
R Drechsler, A Sarabi, M Theobald, B Becker, MA Perkowski
Proceedings of the 31st annual Design Automation Conference, 415-419, 1994
Binary decision diagrams: theory and implementation
R Drechsler, B Becker
Springer Science & Business Media, 2013
A definition and classification of timing anomalies
J Reineke, B Wachter, S Thesing, R Wilhelm, I Polian, J Eisinger, ...
6th International Workshop on Worst-Case Execution Time Analysis (WCET'06), 2006
How robust is the n-cube?
B Becker, HU Simon
Information and Computation 77 (2), 162-178, 1988
Genetic algorithm for variable ordering of OBDDs
R Drechsler, B Becker, N Göckel
IEE Proceedings-Computers and Digital Techniques 143 (6), 364-368, 1996
Multi-objective optimisation based on relation favour
N Drechsler, R Drechsler, B Becker
International conference on evolutionary multi-criterion optimization, 154-166, 2001
A family of logical fault models for reversible circuits
I Polian, T Fiehn, B Becker, JP Hayes
14th Asian Test Symposium (ATS'05), 422-427, 2005
Multithreaded SAT solving
M Lewis, T Schubert, B Becker
2007 Asia and South Pacific Design Automation Conference, 926-931, 2007
Fast OFDD-based minimization of fixed polarity Reed-Muller expressions
R Drechsler, M Theobald, B Becker
IEEE Transactions on Computers 45 (11), 1294-1299, 1996
X-masking during logic BIST and its impact on defect coverage
Y Tang, HJ Wunderlich, H Vranken, F Hapke, M Wittke, P Engelke, ...
2004 International Conferce on Test, 442-451, 2004
K* BMDs: A new data structure for verification
R Drechsler, B Becker, S Ruppertz
Proceedings ED&TC European Design and Test Conference, 2-8, 1996
Checking equivalence for partial implementations
B Becker, C Scholl
Equivalence Checking of Digital Circuits, 145-167, 2004
Testing for missing-gate faults in reversible circuits
JP Hayes, I Polian, B Becker
13th Asian test symposium, 100-105, 2004
Simulating resistive-bridging and stuck-at faults
P Engelke, I Polian, M Renovell, B Becker
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006
On the relation between BDDs and FDDs
B Becker, R Drechsler, R Werchner
Latin American Symposium on Theoretical Informatics, 72-83, 1995
PaMiraXT: Parallel SAT solving with threads and message passing
T Schubert, M Lewis, B Becker
Journal on Satisfiability, Boolean Modeling and Computation 6 (4), 203-222, 2010
An analysis framework for transient-error tolerance
JP Hayes, I Polian, B Becker
25th IEEE VLSI Test Symposium (VTS'07), 249-255, 2007
How many decomposition types do we need?[decision diagrams]
B Becker, R Drechsler
Proceedings the European Design and Test Conference. ED&TC 1995, 438-443, 1995
Sigref–a symbolic bisimulation tool box
R Wimmer, M Herbstritt, H Hermanns, K Strampp, B Becker
International Symposium on Automated Technology for Verification and …, 2006
Power droop testing
I Polian, A Czutro, S Kundu, B Becker
2006 International Conference on Computer Design, 243-250, 2006
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