Robert Cohn
Robert Cohn
Verified email at intel.com
Title
Cited by
Cited by
Year
Pin: building customized program analysis tools with dynamic instrumentation
CK Luk, R Cohn, R Muth, H Patil, A Klauser, G Lowney, S Wallace, ...
Acm sigplan notices 40 (6), 190-200, 2005
42712005
Warp: an integrated solution of high-speed parallel computing
S Borkar, R Cohn, G Cox, S Gleason, T Gross
Proceedings of the 1988 ACM/IEEE conference on Supercomputing, 330-339, 1988
4741988
Pinpointing representative portions of large Intel® Itanium® programs with dynamic instrumentation
H Patil, R Cohn, M Charney, R Kapoor, A Sun, A Karunanidhi
37th International Symposium on Microarchitecture (MICRO-37'04), 81-92, 2004
3542004
Supporting systolic and memory communication in iWarp
S Borkar, R Cohn, G Cox, T Gross, HT Kung, M Lam, M Levine, B Moore, ...
ACM SIGARCH Computer Architecture News 18 (2SI), 70-81, 1990
2621990
CMP $ im: A Pin-based on-the-fly multi-core cache simulator
A Jaleel, RS Cohn, CK Luk, B Jacob
Proceedings of the Fourth Annual Workshop on Modeling, Benchmarking and …, 2008
1912008
Pin: a binary instrumentation tool for computer architecture research and education
VJ Reddi, A Settle, DA Connors, RS Cohn
Proceedings of the 2004 workshop on Computer architecture education: held in …, 2004
1632004
Analyzing parallel programs with pin
M Bach, M Charney, R Cohn, E Demikhovsky, T Devor, K Hazelwood, ...
Computer 43 (3), 34-41, 2010
1322010
Spike: An optimizer for Alpha/NT executables
R Cohn, D Goodwin, PG Lowney, N Rubin
USENIX Windows NT Workshop, 17-24, 1997
1031997
User transparent mechanism for profile feedback optimization
DW Goodwin, RS Cohn, PG Lowney, N Rubin
US Patent 6,158,049, 2000
922000
Optimizing alpha executables on windows nt with spike
RS Cohn, DW Goodwin, PG Lowney, N Rubin
Digital Technical Journal 9, 3-20, 1997
811997
Hot cold optimization of large Windows/NT applications
R Cohn, PG Lowney
Proceedings of the 29th Annual IEEE/ACM International Symposium on …, 1996
801996
Code layout optimizations for transaction processing workloads
A Ramirez, LA Barroso, K Gharachorloo, R Cohn, J Larriba-Pey, ...
ACM SIGARCH Computer Architecture News 29 (2), 155-164, 2001
772001
Architecture and compiler tradeoffs for a long instruction wordprocessor
R Cohn, T Gross, M Lam
Proceedings of the third international conference on Architectural support …, 1989
681989
Automatic logging of operating system effects to guide application-level architecture simulation
S Narayanasamy, C Pereira, H Patil, R Cohn, B Calder
Proceedings of the joint international conference on Measurement and …, 2006
672006
Ispike: a post-link optimizer for the Intel/spl reg/Itanium/spl reg/architecture
CK Luk, R Muth, H Patil, R Cohn, G Lowney
International Symposium on Code Generation and Optimization, 2004. CGO 2004 …, 2004
642004
Software mechanism for reducing exceptions generated by speculatively scheduled instructions
R Cohn, MC Adler, PG Lowney
US Patent 5,901,308, 1999
611999
Analyzing dynamic binary instrumentation overhead
GR Uh, R Cohn, B Yadavalli, R Peri, R Ayyagari
WBIA workshop at ASPLOS, 2006
542006
VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization
H Kim, JA Joao, O Mutlu, CJ Lee, YN Patt, R Cohn
ACM SIGARCH Computer Architecture News 35 (2), 424-435, 2007
532007
Profile-guided post-link stride prefetching
CK Luk, R Muth, H Patil, R Weiss, PG Lowney, R Cohn
Proceedings of the 16th international conference on Supercomputing, 167-178, 2002
482002
Mechanism for re-writing an executable having mixed code and data
PG Lowney, DW Goodwin, R Cohn
US Patent 6,324,689, 2001
482001
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