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Hiroki Matsutani
Hiroki Matsutani
Dept of ICS, Keio University
E-mail confirmado em arc.ics.keio.ac.jp - Página inicial
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A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface
N Miura, Y Koizumi, E Sasaki, Y Take, H Matsutani, T Kuroda, H Amano, ...
2013 IEEE COOL Chips XVI, 1-3, 2013
1872013
A case for random shortcut topologies for HPC interconnects
M Koibuchi, H Matsutani, H Amano, DF Hsu, H Casanova
ACM Sigarch Computer Architecture News 40 (3), 177-188, 2012
1862012
A lightweight fault-tolerant mechanism for network-on-chip
M Koibuchi, H Matsutani, H Amano, TM Pinkston
Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), 13-22, 2008
1802008
Prediction router: Yet another low latency on-chip router architecture
H Matsutani, M Koibuchi, H Amano, T Yoshinaga
2009 IEEE 15th International Symposium on High Performance Computer …, 2009
1352009
Run-time power gating of on-chip routers using look-ahead routing
H Matsutani, M Koibuchi, H Amano, D Wang
2008 Asia and South Pacific Design Automation Conference, 55-60, 2008
1312008
Tightly-coupled multi-layer topologies for 3-D NoCs
H Matsutani, M Koibuchi, H Amano
2007 International Conference on Parallel Processing (ICPP 2007), 75-75, 2007
1002007
Ultra fine-grained run-time power gating of on-chip routers for CMPs
H Matsutani, M Koibuchi, D Ikebuchi, K Usami, H Nakamura, H Amano
2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip, 61-68, 2010
932010
A neural network-based on-device learning anomaly detector for edge devices
M Tsukada, M Kondo, H Matsutani
IEEE Transactions on Computers 69 (7), 1027-1044, 2020
812020
3D NoC with inductive-coupling links for building-block SiPs
Y Take, H Matsutani, D Sasaki, M Koibuchi, T Kuroda, H Amano
IEEE Transactions on Computers 63 (3), 748-763, 2012
782012
Adding slow-silent virtual channels for low-power on-chip networks
H Matsutani, M Koibuchi, D Wang, H Amano
Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), 23-32, 2008
752008
AxNoC: Low-power approximate network-on-chips using critical-path isolation
AB Ahmed, D Fujiki, H Matsutani, M Koibuchi, H Amano
2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 1-8, 2018
632018
Low-latency wireless 3D NoCs via randomized shortcut chips
H Matsutani, M Koibuchi, I Fujiwara, T Kagami, Y Take, T Kuroda, ...
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014
592014
A case for wireless 3D NoCs for CMPs
H Matsutani, P Bogdan, R Marculescu, Y Take, D Sasaki, H Zhang, ...
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 23-28, 2013
582013
Accelerating blockchain search of full nodes using GPUs
S Morishima, H Matsutani
2018 26th Euromicro International Conference on Parallel, Distributed and …, 2018
532018
Layout-conscious random topologies for HPC off-chip interconnects
M Koibuchi, I Fujiwara, H Matsutani, H Casanova
2013 IEEE 19th International Symposium on High Performance Computer …, 2013
532013
A scalable 3D heterogeneous multicore with an inductive ThruChip interface
N Miura, Y Koizumi, Y Take, H Matsutani, T Kuroda, H Amano, ...
IEEE Micro 33 (6), 6-15, 2013
522013
Performance, cost, and energy evaluation of fat h-tree: A cost-efficient tree-based on-chip network
H Matsutani, M Koibuchi, H Amano
2007 IEEE International Parallel and Distributed Processing Symposium, 1-10, 2007
512007
The dependable responsive multithreaded processor for distributed real-time systems
K Suito, R Ueda, K Fujii, T Kogo, H Matsutani, N Yamasaki
IEEE Micro 32 (6), 52-61, 2012
502012
Performance, area, and power evaluations of ultrafine-grained run-time power-gating routers for CMPs
H Matsutani, M Koibuchi, D Ikebuchi, K Usami, H Nakamura, H Amano
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011
452011
Fat H-Tree: A cost-efficient tree-based on-chip network
H Matsutani, M Koibuchi, Y Yamada, DF Hsu, H Amano
IEEE Transactions on Parallel and Distributed Systems 20 (8), 1126-1141, 2008
412008
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