| Logical modelling of delay degradation effect in static CMOS gates MJ Bellido-Diaz, J Juan-Chico, AJ Acosta, M Valencia, JL Huertas IEE Proceedings-Circuits, Devices and Systems 147 (2), 107-117, 2000 | 89 | 2000 |
| Simple binary random number generator MJ Bellido, AJ Acosta, M Valencia, A Barriga, JL Huertas Electronics Letters 7 (28), 617-618, 1992 | 42 | 1992 |
| Logic-timing simulation and the degradation delay model MJ Bellido, JJ Chico, M Valencia Imperial College Press, 2006 | 36 | 2006 |
| SODS: A new CMOS differential-type structure AJ Acosta, M Valencia, A Barriga, MJ Bellido, JL Huertas IEEE journal of solid-state circuits 30 (7), 835-838, 1995 | 32 | 1995 |
| Problemas de circuitos y sistemas digitales CB Oliva, MJB Díaz, AJM Cantero, MPP Fernández, MV Barrero McGraw-Hill, 1997 | 28 | 1997 |
| Vulnerability analysis of trivium fpga implementations FE Potestad-Ordóñez, CJ Jiménez-Fernández, M Valencia-Barrero IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (12 …, 2017 | 26 | 2017 |
| High radix implementation of Montgomery multipliers with CSA G Sassaw, CJ Jimenez, M Valencia 2010 International Conference on Microelectronics, 315-318, 2010 | 26 | 2010 |
| Degradation delay model extension to CMOS gates J Juan-Chico, MJ Bellido, P Ruiz-de-Clavijo, AJ Acosta, M Valencia Integrated Circuit Design: Power and Timing Modeling, Optimization and …, 2000 | 23 | 2000 |
| A simple binary random number generator: new approaches for cmos vlsi MJ Bellido, AJ Acosta, M Valencia, A Barriga, JL Huertas [1992] Proceedings of the 35th Midwest Symposium on Circuits and Systems …, 1992 | 21 | 1992 |
| Asynchronous modular arbiter Calvo, Acha, Valencia IEEE transactions on computers 100 (1), 67-70, 1986 | 21 | 1986 |
| Fault attack on FPGA implementations of Trivium stream cipher FE Potestad-Ordóñez, CJ Jiménez-Fernández, M Valencia-Barrero 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 562-565, 2016 | 19 | 2016 |
| HALOTIS: High accuracy logic timing simulator with inertial and degradation delay model PR de Clavijo Vazquez, J Juan-Chico, MJ Bellido, A Acosta, M Valencia Proceedings Design, Automation and Test in Europe. Conference and Exhibition …, 2001 | 19 | 2001 |
| Design and characterisation of a CMOS VLSI self-timed multiplier architecture based on a bit-level pipelined-array structure AJ Acosta, R Jiménez, A Barriga, MJ Bellido, M Valencia, JL Huertas IEE Proceedings-Circuits, Devices and Systems 145 (4), 247-253, 1998 | 17 | 1998 |
| Analysis of metastable operation in a CMOS dynamic D-latch J Juan-Chico, MJ Bellido, AJ Acosta, M Valencia, JL Huertas Analog Integrated Circuits and Signal Processing 14, 143-157, 1997 | 17 | 1997 |
| Measurement of the switching activity of CMOS digital circuits at the gate level C Baena, J Juan-Chico, MJ Bellido, PR de Clavijo, CJ Jimenez, ... Integrated Circuit Design. Power and Timing Modeling, Optimization and …, 2002 | 16 | 2002 |
| Multiradix trivium implementations for low-power IoT hardware JM Mora-Gutierrez, CJ Jiménez-Fernández, M Valencia-Barrero IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (12 …, 2017 | 15 | 2017 |
| Low power implementation of Trivium stream cipher JM Mora-Gutierrez, CJ Jiménez-Fernández, M Valencia-Barrero Integrated Circuit and System Design. Power and Timing Modeling …, 2013 | 15 | 2013 |
| Delay degradation effect in submicronic CMOS inverters J Juan Chico, MJ Bellido Díaz, AJ Acosta Jiménez, Á Barriga Barros, ... PATMOS 1997: 6th International Workshop on Power and Timing Modeling …, 1997 | 15 | 1997 |
| Modular asynchronous arbiter insensitive to metastability M Valencia, MJ Bellido, JL Huertas, AJ Acosta, S Sánchez-Solano IEEE transactions on computers 44 (12), 1456-1461, 1995 | 13 | 1995 |
| Development of untethered SU-8 polymer scratch drive microrobots M Valencia, T Atallah, D Castro, D Conchouso, M Dosari, R Hammad, ... 2011 IEEE 24th International Conference on Micro Electro Mechanical Systems …, 2011 | 11 | 2011 |
