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Manuel Valencia-Barrero, M. Valencia
Manuel Valencia-Barrero, M. Valencia
Profesor de Tecnologia Electronica de Universidad de Sevilla, miembro del IMSE-CNM
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Logical modelling of delay degradation effect in static CMOS gates
MJ Bellido-Diaz, J Juan-Chico, AJ Acosta, M Valencia, JL Huertas
IEE Proceedings-Circuits, Devices and Systems 147 (2), 107-117, 2000
912000
Simple binary random number generator
MJ Bellido, AJ Acosta, M Valencia, A Barriga, JL Huertas
Electronics Letters 7 (28), 617-618, 1992
421992
Logic-timing simulation and the degradation delay model
MJ Bellido, JJ Chico, M Valencia
Imperial College Press, 2006
372006
SODS: A new CMOS differential-type structure
AJ Acosta, M Valencia, A Barriga, MJ Bellido, JL Huertas
IEEE journal of solid-state circuits 30 (7), 835-838, 1995
331995
High radix implementation of Montgomery multipliers with CSA
G Sassaw, CJ Jimenez, M Valencia
2010 International Conference on Microelectronics, 315-318, 2010
292010
Vulnerability analysis of trivium fpga implementations
FE Potestad-Ordóñez, CJ Jiménez-Fernández, M Valencia-Barrero
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (12 …, 2017
252017
Problemas de circuitos y sistemas digitales
CB Oliva, MJB Díaz, AJM Cantero, MPP Fernández, MV Barrero
McGraw-Hill, 1997
241997
Degradation delay model extension to CMOS gates
J Juan-Chico, MJ Bellido, P Ruiz-de-Clavijo, AJ Acosta, M Valencia
Integrated Circuit Design: Power and Timing Modeling, Optimization and …, 2000
232000
Asynchronous modular arbiter
Calvo, Acha, Valencia
IEEE transactions on computers 100 (1), 67-70, 1986
211986
A simple binary random number generator: new approaches for cmos vlsi
MJ Bellido, AJ Acosta, M Valencia, A Barriga, JL Huertas
[1992] Proceedings of the 35th Midwest Symposium on Circuits and Systems …, 1992
201992
Fault attack on FPGA implementations of Trivium stream cipher
FE Potestad-Ordóñez, CJ Jiménez-Fernández, M Valencia-Barrero
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 562-565, 2016
192016
HALOTIS: High accuracy logic timing simulator with inertial and degradation delay model
PR de Clavijo Vazquez, J Juan-Chico, MJ Bellido, A Acosta, M Valencia
Proceedings Design, Automation and Test in Europe. Conference and Exhibition …, 2001
192001
Analysis of metastable operation in a CMOS dynamic D-latch
J Juan-Chico, MJ Bellido, AJ Acosta, M Valencia, JL Huertas
Analog Integrated Circuits and Signal Processing 14, 143-157, 1997
181997
Design and characterisation of a CMOS VLSI self-timed multiplier architecture based on a bit-level pipelined-array structure
AJ Acosta, R Jiménez, A Barriga, MJ Bellido, M Valencia, JL Huertas
IEE Proceedings-Circuits, Devices and Systems 145 (4), 247-253, 1998
171998
Measurement of the switching activity of CMOS digital circuits at the gate level
C Baena, J Juan-Chico, MJ Bellido, PR de Clavijo, CJ Jimenez, ...
Integrated Circuit Design. Power and Timing Modeling, Optimization and …, 2002
162002
Multiradix trivium implementations for low-power IoT hardware
JM Mora-Gutierrez, CJ Jiménez-Fernández, M Valencia-Barrero
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (12 …, 2017
152017
Low power implementation of Trivium stream cipher
JM Mora-Gutierrez, CJ Jiménez-Fernández, M Valencia-Barrero
Integrated Circuit and System Design. Power and Timing Modeling …, 2013
152013
Delay degradation effect in submicronic CMOS inverters
J Juan Chico, MJ Bellido Díaz, AJ Acosta Jiménez, Á Barriga Barros, ...
PATMOS 1997: 6th International Workshop on Power and Timing Modeling …, 1997
151997
Modular asynchronous arbiter insensitive to metastability
M Valencia, MJ Bellido, JL Huertas, AJ Acosta, S Sánchez-Solano
IEEE transactions on computers 44 (12), 1456-1461, 1995
131995
Development of untethered SU-8 polymer scratch drive microrobots
M Valencia, T Atallah, D Castro, D Conchouso, M Dosari, R Hammad, ...
2011 IEEE 24th International Conference on Micro Electro Mechanical Systems …, 2011
112011
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