Miquel Moreto
Miquel Moreto
Ramon y Cajal Fellow at UPC and Associate Researcher at BSC
Correu electrònic verificat a ac.upc.edu - Pàgina d'inici
Citada per
Citada per
The Rocket Chip Generator
K Asanovi, R Avizienis, J Bachrach, S Beamer, D Biancolin, C Celio, ...
A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness
H Cook, M Moreto, S Bird, K Dao, DA Patterson, K Asanovic
ACM SIGARCH Computer Architecture News 41 (3), 308-319, 2013
Multicore resource management
KJ Nesbit, M Moreto, FJ Cazorla, A Ramirez, M Valero, JE Smith
IEEE micro 28 (3), 6-16, 2008
Tessellation: Refactoring the OS around explicit resource containers with continuous adaptation
JA Colmenares, G Eads, S Hofmeyr, S Bird, M Moretó, D Chou, ...
Proceedings of the 50th Annual Design Automation Conference, 1-10, 2013
Modeling toroidal networks with the Gaussian integers
C Martínez, R Beivide, E Stafford, M Moreto, EM Gabidulin
IEEE Transactions on Computers 57 (8), 1046-1056, 2008
FlexDCP: a QoS framework for CMP architectures
M Moreto, FJ Cazorla, A Ramirez, R Sakellariou, M Valero
ACM SIGOPS Operating Systems Review 43 (2), 86-96, 2009
Adapting cache partitioning algorithms to pseudo-lru replacement policies
K Kędzierski, M Moreto, FJ Cazorla, M Valero
2010 IEEE International Symposium on Parallel & Distributed Processing …, 2010
MLP-aware dynamic cache partitioning
M Moreto, FJ Cazorla, A Ramirez, M Valero
International Conference on High-Performance Embedded Architectures and …, 2008
Twisted torus topologies for enhanced interconnection networks
JM Camara, M Moreto, E Vallejo, R Beivide, J Miguel-Alonso, C Martínez, ...
IEEE Transactions on Parallel and Distributed Systems 21 (12), 1765-1778, 2010
PARSECSs: Evaluating the impact of task parallelism in the PARSEC benchmark suite
D Chasapis, M Casas, M Moretó, R Vidal, E Ayguadé, J Labarta, M Valero
ACM Transactions on Architecture and Code Optimization (TACO) 12 (4), 1-22, 2015
Optimal task assignment in multithreaded processors: A statistical approach
P Radojković, V Čakarević, M Moretó, J Verdú, A Pajuelo, FJ Cazorla, ...
ACM SIGPLAN Notices 47 (4), 235-248, 2012
Runtime-aware architectures: A first approach
M Valero, M Moreto, M Casas, E Ayguade, J Labarta
Supercomputing frontiers and innovations 1 (1), 29-44, 2014
Task scheduling techniques for asymmetric multi-core systems
K Chronaki, A Rico, M Casas, M Moretó, RM Badia, E Ayguadé, J Labarta, ...
IEEE Transactions on Parallel and Distributed Systems 28 (7), 2074-2087, 2016
Runtime-aware architectures
M Casas, M Moreto, L Alvarez, E Castillo, D Chasapis, T Hayes, ...
European Conference on Parallel Processing, 16-27, 2015
Exploiting asynchrony from exact forward recovery for due in iterative solvers
L Jaulmes, M Casas, M Moretó, E Ayguadé, J Labarta, M Valero
SC'15: Proceedings of the International Conference for High Performance …, 2015
Dense Gaussian networks: Suitable topologies for on-chip multiprocessors
C Martínez, E Vallejo, R Beivide, C Izu, M Moretó
International Journal of Parallel Programming 34 (3), 193-211, 2006
Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures
L Alvarez, L Vilanova, M Moreto, M Casas, M Gonzàlez, X Martorell, ...
2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture …, 2015
Simulating whole supercomputer applications
J Gonzalez, J Gimenez, M Casas, M Moreto, A Ramirez, J Labarta, ...
IEEE micro 31 (3), 32-45, 2011
Explaining dynamic cache partitioning speed ups
M Moreto Planas, F Cazorla, A Ramírez Bellido, M Valero Cortés
IEEE Computer Architecture Letters 6 (1), 1-4, 2007
MUSA: a multi-level simulation approach for next-generation HPC machines
T Grass, C Allande, A Armejach, A Rico, E Ayguadé, J Labarta, M Valero, ...
SC'16: Proceedings of the International Conference for High Performance …, 2016
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