| The Rocket Chip Generator K Asanovi, R Avizienis, J Bachrach, S Beamer, D Biancolin, C Celio, ... | 611 | 2016 |
| A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness H Cook, M Moreto, S Bird, K Dao, DA Patterson, K Asanovic ACM SIGARCH Computer Architecture News 41 (3), 308-319, 2013 | 159 | 2013 |
| Multicore resource management KJ Nesbit, M Moreto, FJ Cazorla, A Ramirez, M Valero, JE Smith IEEE micro 28 (3), 6-16, 2008 | 142 | 2008 |
| The gem5 simulator: Version 20.0+ J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ... arXiv preprint arXiv:2007.03152, 2020 | 128 | 2020 |
| Tessellation: Refactoring the OS around explicit resource containers with continuous adaptation JA Colmenares, G Eads, S Hofmeyr, S Bird, M Moretó, D Chou, ... Proceedings of the 50th Annual Design Automation Conference, 1-10, 2013 | 84 | 2013 |
| Adapting cache partitioning algorithms to pseudo-lru replacement policies K Kędzierski, M Moreto, FJ Cazorla, M Valero 2010 IEEE International Symposium on Parallel & Distributed Processing …, 2010 | 78 | 2010 |
| Modeling toroidal networks with the Gaussian integers C Martínez, R Beivide, E Stafford, M Moretó, EM Gabidulin IEEE Transactions on Computers 57 (8), 1046-1056, 2008 | 78 | 2008 |
| FlexDCP: a QoS framework for CMP architectures M Moreto, FJ Cazorla, A Ramirez, R Sakellariou, M Valero ACM SIGOPS Operating Systems Review 43 (2), 86-96, 2009 | 74 | 2009 |
| Fast gap-affine pairwise alignment using the wavefront algorithm S Marco-Sola, JC Moure, M Moreto, A Espinosa Bioinformatics 37 (4), 456-463, 2021 | 73 | 2021 |
| PARSECSs: Evaluating the impact of task parallelism in the PARSEC benchmark suite D Chasapis, M Casas, M Moretó, R Vidal, E Ayguadé, J Labarta, M Valero ACM Transactions on Architecture and Code Optimization (TACO) 12 (4), 1-22, 2015 | 72 | 2015 |
| Twisted torus topologies for enhanced interconnection networks JM Camara, M Moreto, E Vallejo, R Beivide, J Miguel-Alonso, C Martínez, ... IEEE Transactions on Parallel and Distributed Systems 21 (12), 1765-1778, 2010 | 72 | 2010 |
| MLP-aware dynamic cache partitioning M Moreto, FJ Cazorla, A Ramirez, M Valero High Performance Embedded Architectures and Compilers: Third International …, 2008 | 72 | 2008 |
| Task scheduling techniques for asymmetric multi-core systems K Chronaki, A Rico, M Casas, M Moretó, RM Badia, E Ayguadé, J Labarta, ... IEEE Transactions on Parallel and Distributed Systems 28 (7), 2074-2087, 2016 | 62 | 2016 |
| Optimal task assignment in multithreaded processors: A statistical approach P Radojković, V Čakarević, M Moretó, J Verdú, A Pajuelo, FJ Cazorla, ... ACM SIGPLAN Notices 47 (4), 235-248, 2012 | 56 | 2012 |
| Runtime-aware architectures: A first approach M Valero, M Moreto, M Casas, E Ayguade, J Labarta Supercomputing frontiers and innovations 1 (1), 29-44, 2014 | 49 | 2014 |
| Exploiting asynchrony from exact forward recovery for due in iterative solvers L Jaulmes, M Casas, M Moretó, E Ayguadé, J Labarta, M Valero Proceedings of the International Conference for High Performance Computing …, 2015 | 43 | 2015 |
| Runtime-aware architectures M Casas, M Moreto, L Alvarez, E Castillo, D Chasapis, T Hayes, ... Euro-Par 2015: Parallel Processing: 21st International Conference on …, 2015 | 43 | 2015 |
| Dense Gaussian networks: Suitable topologies for on-chip multiprocessors C Martínez, E Vallejo, R Beivide, C Izu, M Moretó International Journal of Parallel Programming 34 (3), 193-211, 2006 | 43 | 2006 |
| Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures L Alvarez, L Vilanova, M Moreto, M Casas, M Gonzàlez, X Martorell, ... Proceedings of the 42nd Annual International Symposium on Computer …, 2015 | 42 | 2015 |
| MUSA: a multi-level simulation approach for next-generation HPC machines T Grass, C Allande, A Armejach, A Rico, E Ayguadé, J Labarta, M Valero, ... SC'16: Proceedings of the International Conference for High Performance …, 2016 | 40 | 2016 |
Mateo ValeroProfessor and director of the Barcelona Supercomputing CenterVerified email at bsc.es
