| The EPFL logic synthesis libraries M Soeken, H Riener, W Haaswijk, E Testa, B Schmitt, G Meuli, F Mozafari, ... arXiv preprint arXiv:1805.05121, 2018 | 104 | 2018 |
| Deep learning for logic optimization algorithms W Haaswijk, E Collins, B Seguin, M Soeken, F Kaplan, S Süsstrunk, ... 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2018 | 90 | 2018 |
| A novel basis for logic rewriting W Haaswijk, M Soeken, L Amarú, PE Gaillardon, G De Micheli 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 151-156, 2017 | 74 | 2017 |
| On-the-fly and DAG-aware: Rewriting Boolean networks with exact synthesis H Riener, W Haaswijk, A Mishchenko, G De Micheli, M Soeken 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2019 | 62 | 2019 |
| SAT-based exact synthesis: Encodings, topology families, and parallelism W Haaswijk, M Soeken, A Mishchenko, G De Micheli IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 54 | 2019 |
| SAT based exact synthesis using DAG topology families W Haaswijk, A Mishchenko, M Soeken, G De Micheli Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 42 | 2018 |
| Scalable generic logic synthesis: One approach to rule them all H Riener, E Testa, W Haaswijk, A Mishchenko, L Amarù, G De Micheli, ... Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 37 | 2019 |
| Practical exact synthesis M Soeken, W Haaswijk, E Testa, A Mishchenko, LG Amarù, RK Brayton, ... 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 309-314, 2018 | 32 | 2018 |
| Mapping monotone Boolean functions into majority E Testa, M Soeken, LG Amarù, W Haaswijk, G De Micheli IEEE Transactions on Computers 68 (5), 791-797, 2018 | 18 | 2018 |
| LUT mapping and optimization for majority-inverter graphs WJ Haaswijk, M Soeken, L Amaru, PE Gaillardon, G De Micheli Proceedings of the 25th International Workshop on Logic & Synthesis (IWLS), 2016 | 18 | 2016 |
| Classifying functions with exact synthesis W Haaswijk, E Testa, M Soeken, G De Micheli 2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL), 272-277, 2017 | 16 | 2017 |
| One-pass synthesis for field-coupled nanocomputing technologies M Walter, W Haaswijk, R Wille, FS Torres, R Drechsler Proceedings of the 26th Asia and South Pacific Design Automation Conference …, 2021 | 15 | 2021 |
| A novel basis for logic optimization W Haaswijk, M Soeken, LG Amarù, PE Gaillardon, G De Micheli Asia and South Pacific Design Automation Conference, 151-156, 2017 | 11 | 2017 |
| Exact synthesis of boolean functions in majority-of-five forms Z Chu, W Haaswijk, M Soeken, Y Xia, L Wang, G De Micheli 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019 | 10 | 2019 |
| The EPFL Logic Synthesis Libraries (2019) M Soeken, H Riener, W Haaswijk, E Testa, B Schmitt, G Meuli, F Mozafari, ... arXiv preprint arXiv:1805.05121, 0 | 7 | |
| SAT-based exact synthesis for multi-level logic networks WJ Haaswijk EPFL, 2019 | 5 | 2019 |
| Multi-level logic benchmarks: An exactness study L Amarú, M Soeken, W Haaswijk, E Testa, P Vuillod, J Luo, PE Gaillardon, ... 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 157-162, 2017 | 5 | 2017 |
| NEM relay design with biconditional binary decision diagrams W Haaswijk, L Amaru, PE Gaillardon, G De Micheli Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale …, 2015 | 4 | 2015 |
| Logic optimization of majority-inverter graphs H Riener, E Testa, W Haaswijk, A Mishchenko, L Amarú, G De Micheli, ... MBMV 2019; 22nd Workshop-Methods and Description Languages for Modelling and …, 2019 | 3 | 2019 |
| Integrated ESOP refactoring for industrial designs W Haaswijk, LG Amaru, P Vuillod, J Luo, M Soeken, G De Micheli 2018 25th IEEE International Conference on Electronics, Circuits and Systems …, 2018 | 3 | 2018 |
Mathias SoekenMicrosoftDirección de correo verificada de epfl.ch
