| A new family of high. performance parallel decimal multipliers A Vázquez, E Antelo, P Montuschi 18th IEEE Symposium on Computer Arithmetic (ARITH'07), 195-204, 2007 | 168 | 2007 |
| High performance rotation architectures based on the radix-4 CORDIC algorithm E Antelo, J Villalba, JD Bruguera, EL Zapata IEEE Transactions on Computers 46 (8), 855-870, 1997 | 164 | 1997 |
| Improved design of high-performance parallel decimal multipliers A Vazquez, E Antelo, P Montuschi IEEE Transactions on Computers 59 (5), 679-693, 2009 | 124 | 2009 |
| Reducing the computation time in (short bit-width) two's complement multipliers F Lamberti, N Andrikos, E Antelo, P Montuschi IEEE transactions on computers 60 (2), 148-156, 2010 | 77 | 2010 |
| High-throughput CORDIC-based geometry operations for 3D computer graphics T Lang, E Antelo IEEE Transactions on Computers 54 (3), 347-361, 2005 | 66 | 2005 |
| Improved 64-bit radix-16 booth multiplier based on partial product array height reduction E Antelo, P Montuschi, A Nannarelli IEEE Transactions on Circuits and Systems I: Regular Papers 64 (2), 409-418, 2016 | 58 | 2016 |
| A low-latency pipelined 2D and 3D CORDIC processors E Antelo, J Villalba, EL Zapata IEEE Transactions on Computers 57 (3), 404-417, 2008 | 56 | 2008 |
| Conditional speculative decimal addition Á Vázquez, E Antelo 7th Conference on Real Numbers and Computers (RNC 7), 47-57, 2006 | 56 | 2006 |
| CORDIC architectures with parallel compensation of the scale factor J Villalba, JA Hidalgo, EL Zapata, E Antelo, JD Bruguera Proceedings The International Conference on Application Specific Array …, 1995 | 52 | 1995 |
| Unified mixed radix 2-4 redundant CORDIC processor E Antelo, JD Bruguera, EL Zapata IEEE transactions on Computers 45 (9), 1068-1073, 1996 | 50 | 1996 |
| Digit-recurrence dividers with reduced logical depth E Antelo, T Lang, P Montuschi, A Nannarelli IEEE Transactions on Computers 54 (7), 837-851, 2005 | 46 | 2005 |
| A radix-10 SRT divider based on alternative BCD codings A Vazquez, E Antelo, P Montuschi 2007 25th International Conference on Computer Design, 280-287, 2007 | 40 | 2007 |
| Design of a pipelined radix 4 CORDIC processor JD Bruguera, E Antelo, EL Zapata Parallel computing 19 (7), 729-744, 1993 | 38 | 1993 |
| Fast radix-10 multiplication using redundant BCD codes A Vazquez, E Antelo, JD Bruguera IEEE transactions on computers 63 (8), 1902-1914, 2014 | 37 | 2014 |
| Very-high radix circular CORDIC: Vectoring and unified rotation/vectoring E Antelo, T Lang, JD Bruguera IEEE Transactions on Computers 49 (7), 727-739, 2000 | 37 | 2000 |
| Computation of/spl radic/(x/d) in a very high radix combined division/square-root unit with scaling and selection by rounding E Antelo, T Lang, JD Bruguera IEEE Transactions on Computers 47 (2), 152-161, 1998 | 36 | 1998 |
| Very-high radix CORDIC rotation based on selection by rounding E Antelo, T Lang, JD Bruguera Journal of VLSI signal processing systems for signal, image and video …, 2000 | 35 | 2000 |
| VLSI implementation of an edge detector based on Sobel operator M Boo, E Antelo, JD Bruguera Proceedings of Twentieth Euromicro Conference. System Architecture and …, 1994 | 30 | 1994 |
| A high-performance significand BCD adder with IEEE 754-2008 decimal rounding A Vázquez, E Antelo 2009 19th IEEE Symposium on Computer Arithmetic, 135-144, 2009 | 29 | 2009 |
| Error analysis and reduction for angle calculation using the CORDIC algorithm E Antelo, JD Bruguera, T Lang, EL Zapata IEEE transactions on computers 46 (11), 1264-1271, 1997 | 27 | 1997 |
