A low power radix-2 FFT accelerator for FPGA S Mookherjee, L DeBrunner, V DeBrunner 2015 49th Asilomar Conference on Signals, Systems and Computers, 447-451, 2015 | 18 | 2015 |
Energy optimization of Application-Specific Instruction-Set Processors by using hardware accelerators in semicustom ICs technology U Meyer-Baese, G Botella, S Mookherjee, E Castillo, A García Microprocessors and Microsystems 36 (2), 127-137, 2012 | 11 | 2012 |
A high throughput and low power radix-4 FFT architecture S Mookherjee, L DeBrunner, V DeBrunner 2014 48th Asilomar Conference on Signals, Systems and Computers, 1266-1270, 2014 | 10 | 2014 |
A hardware efficient technique for linear convolution of finite length sequences S Mookherjee, LS DeBrunner, V DeBrunner 2013 Asilomar Conference on Signals, Systems and Computers, 515-519, 2013 | 10 | 2013 |
Hardware implementation of the Hirschman optimal transform S Mookherjee, LS DeBrunner, V DeBrunner 2012 Conference Record of the Forty Sixth Asilomar Conference on Signals …, 2012 | 8 | 2012 |
NIOS II processor-based acceleration of motion compensation techniques D González, G Botella, S Mookherjee, U Meyer-Bäse, A Meyer-Bäse Independent Component Analyses, Wavelets, Neural Networks, Biosystems, and …, 2011 | 2 | 2011 |
3-D simulation of electronic and ionic transport in PEFC cathodes S Mookherjee, P Andrei, W Zhu, J Zheng 2011 International Semiconductor Device Research Symposium (ISDRS), 1-1, 2011 | | 2011 |