| CMOS digital duty cycle correction circuit for multi-phase clock YC Jang, SJ Bae, HJ Park Electronics Letters 39 (19), 1383-1384, 2003 | 56 | 2003 |
| CMOS sense amplifier-based flip-flop with two NC^ sup 2^ MOS output latches JC Kim, YC Jang, HJ Park Electronics Letters 36 (6), 1, 2000 | 56 | 2000 |
| Digital duty cycle correction circuit and method for multi-phase clock HJ Park, YC Jang, SJ Bae US Patent 6,958,639, 2005 | 44 | 2005 |
| Methods of reducing skew between multiphase signals and related phase correction circuits YC Jang US Patent 7,840,831, 2010 | 38 | 2010 |
| Circuit and method for correcting skew in a plurality of communication channels for communicating with a memory device, memory controller, system and method using the same, and … YC Jang US Patent 8,103,917, 2012 | 31 | 2012 |
| A digital CMOS PWCL with fixed-delay rising edge and digital stability control YC Jang, JH Bae, HJ Park IEEE Transactions on Circuits and Systems II: Express Briefs 53 (10), 1063-1067, 2006 | 21 | 2006 |
| Output circuit having variable output voltage swing level YC Jang US Patent 7,944,232, 2011 | 18 | 2011 |
| Output driver H Chung, YC Jang US Patent 7,463,073, 2008 | 18 | 2008 |
| Apparatuses and method for multi-level communication YC Jang, H Chung US Patent App. 12/230,578, 2009 | 16 | 2009 |
| An 8 Gb/s/pin 9.6 ns row-cycle 288 Mb deca-data rate SDRAM with an I/O error detection scheme K Kim, HJ Chung, WS Kim, M Park, YC Jang, JY Kim, HW Park, U Kang, ... IEEE journal of solid-state circuits 42 (1), 193-200, 2006 | 15 | 2006 |
| A 10-Gbps receiver bridge chip with deserializer for FPGA-based frame grabber supporting MIPI CSI-2 PH Lee, HY Lee, YW Kim, HY Hong, YC Jang IEEE Transactions on Consumer Electronics 63 (3), 209-215, 2017 | 13 | 2017 |
| Clock generating apparatus YC Jang US Patent 7,821,317, 2010 | 13 | 2010 |
| A 1 V 200 kS/s 10-bit Successive Approximation ADC for a Sensor Interface JH Eo, SH Kim, YC Jang IEICE transactions on electronics 94 (11), 1798-1801, 2011 | 12 | 2011 |
| Semiconductor device and method for decreasing noise of output driver YC Jang US Patent App. 11/820,611, 2008 | 12 | 2008 |
| A 6.84 Gbps/lane MIPI C-PHY transceiver bridge chip with level-dependent equalization PH Lee, YC Jang IEEE Transactions on Circuits and Systems II: Express Briefs 67 (11), 2672-2676, 2019 | 11 | 2019 |
| 12-bit 20M-S/s SAR ADC using CR DAC and capacitor calibration E Youn, YC Jang 2018 International SoC Design Conference (ISOCC), 1-2, 2018 | 10 | 2018 |
| Circuit and method for correcting skew in a plurality of communication channels for communicating with a memory device, memory controller, system and method using the same, and … YC Jang US Patent App. 13/347,000, 2012 | 10 | 2012 |
| A true single-phase clocked flip-flop with leakage current compensation HY Lee, YC Jang IEICE Electronics Express 9 (23), 1807-1812, 2012 | 9 | 2012 |
| An 8-bit 200 MS/s CMOS folding/interpolating ADC with a reduced number of preamplifiers using an averaging technique SC Heo, YC Jang, SH Park, HJ Park 15th Annual IEEE International ASIC/SOC Conference, 80-83, 2002 | 9 | 2002 |
| An 8.8-GS/s 6-bit CMOS time-interleaved flash analog-to-digital converter with multi-phase clock generator YC Jang, JH Bae, SH Park, JY Sim, HJ Park IEICE transactions on electronics 90 (6), 1156-1164, 2007 | 8 | 2007 |
