Low-power linear computation using nonlinear ferroelectric tunnel junction memristors R Berdan, T Marukame, K Ota, M Yamaguchi, M Saitoh, S Fujii, J Deguchi, ...
Nature Electronics 3 (5), 259-266, 2020
152 2020 Comparative study of macroscopic quantum tunneling in K Ota, K Hamada, R Takemura, M Ohmaki, T Machi, K Tanabe, M Suzuki, ...
Physical Review B 79 (13), 134505, 2009
46 2009 2019 IEEE Int. Electron Devices Meeting (IEDM) K Ota, M Yamaguchi, R Berdan, T Marukame, Y Nishi, K Matsuo, ...
IEEE, 2019
34 2019 Threshold voltage control by substrate bias in 10-nm-diameter tri-gate nanowire MOSFET on ultrathin BOX K Ota, M Saitoh, C Tanaka, T Numata
IEEE electron device letters 34 (2), 187-189, 2013
30 2013 HfO2 -based FeFET and FTJ for Ferroelectric-Memory Centric 3D LSI towards Low-Power and High-Density Storage and AI Applications M Saitoh, R Ichihara, M Yamaguchi, K Suzuki, K Takano, K Akari, ...
2020 IEEE International Electron Devices Meeting (IEDM), 18.1. 1-18.1. 4, 2020
28 2020 In-memory reinforcement learning with moderately-stochastic conductance switching of ferroelectric tunnel junctions R Berdan, T Marukame, S Kabuyanagi, K Ota, M Saitoh, S Fujii, J Deguchi, ...
2019 Symposium on VLSI Technology, T22-T23, 2019
28 2019 10nm-diameter tri-gate silicon nanowire MOSFETs with enhanced high-field transport and Vth tunability through thin BOX M Saitoh, K Ota, C Tanaka, K Uchida, T Numata
2012 Symposium on VLSI Technology (VLSIT), 11-12, 2012
28 2012 Semiconductor memory device K Ota, T Irisawa, T Kawai, D Matsushita, T Tezuka
US Patent 9,780,170, 2017
27 2017 Semiconductor device and method of manufacturing the same M Saitoh, T Numata, Y Nakabayashi, K Ota
US Patent App. 13/237,697, 2012
27 2012 Understanding of short-channel mobility in tri-gate nanowire MOSFETs and enhanced stress memorization technique for performance improvement M Saitoh, Y Nakabayashi, K Ota, K Uchida, T Numata
2010 International Electron Devices Meeting, 34.3. 1-34.3. 4, 2010
23 2010 Experimental study of self-heating effects in trigate nanowire MOSFETs considering device geometry K Ota, M Saitoh, C Tanaka, Y Nakabayashi, T Numata
IEEE transactions on electron devices 59 (12), 3239-3242, 2012
22 2012 Performance Maximization of In-Memory Reinforcement Learning with Variability-Controlled Hf1-x Zrx O2 Ferroelectric Tunnel Junctions K Ota, M Yamaguchi, R Berdan, T Marukame, Y Nishi, K Matsuo, ...
2019 IEEE International Electron Devices Meeting (IEDM), 6.2. 1-6.2. 4, 2019
20 2019 Experimental study of random telegraph noise in trigate nanowire MOSFETs K Ota, M Saitoh, C Tanaka, D Matsushita, T Numata
IEEE Transactions on Electron Devices 62 (11), 3799-3804, 2015
18 2015 Semiconductor device and method of manufacturing the same K Ota, T Numata, M Saitoh, C Tanaka
US Patent 8,518,769, 2013
18 2013 Performance improvement by stress memorization technique in trigate silicon nanowire MOSFETs M Saitoh, Y Nakabayashi, K Ota, K Uchida, T Numata
IEEE Electron Device Letters 33 (1), 8-10, 2011
17 2011 Systematic study of RTN in nanowire transistor and enhanced RTN by hot carrier injection and negative bias temperature instability K Ota, M Saitoh, C Tanaka, D Matsushita, T Numata
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014
15 2014 Improved state stability of HfO2 ferroelectric tunnel junction by template-induced crystallization and remote scavenging for efficient in-memory reinforcement learning S Fujii, M Yamaguchi, S Kabuyanagi, K Ota, M Saitoh
2020 IEEE Symposium on VLSI Technology, 1-2, 2020
14 2020 Semiconductor device and method of manufacturing the same K Ota, T Numata, M Saitoh, C Tanaka
US Patent 9,530,891, 2016
14 2016 Nonvolatile semiconductor memory device and method of manufacturing the same K Sakuma, K Ota, M Saitoh, C Tanaka, D Matsushita
US Patent 9,502,431, 2016
12 2016 Performance, variability and reliability of silicon tri-gate nanowire MOSFETs M Saitoh, K Ota, C Tanaka, Y Nakabayashi, K Uchida, T Numata
2012 IEEE International Reliability Physics Symposium (IRPS), 6A. 3.1-6A. 3.6, 2012
11 2012 