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Ahmad Yasin
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A top-down method for performance analysis and counters architecture
A Yasin
2014 IEEE International Symposium on Performance Analysis of Systems and …, 2014
3572014
Inside 6th-generation intel core: New microarchitecture code-named skylake
J Doweck, WF Kao, AK Lu, J Mandelblat, A Rahatekar, L Rappoport, ...
IEEE Micro 37 (2), 52-62, 2017
2002017
Deep-dive analysis of the data analytics workload in cloudsuite
A Yasin, Y Ben-Asher, A Mendelson
2014 IEEE International Symposium on Workload Characterization (IISWC), 202-211, 2014
722014
Fine-grain power breakdown of modern out-of-order cores and its implications on skylake-based systems
J Haj-Yihia, A Yasin, YB Asher, A Mendelson
ACM Transactions on Architecture and Code Optimization (TACO) 13 (4), 1-25, 2016
562016
Establishing a base of trust with performance counters for enterprise workloads
A Nowak, A Yasin, A Mendelson, W Zwaenepoel
2015 USENIX Annual Technical Conference (USENIX ATC 15), 541-548, 2015
322015
Intel alder lake cpu architectures
E Rotem, A Yoaz, L Rappoport, SJ Robinson, JY Mandelblat, A Gihon, ...
IEEE Micro 42 (3), 13-19, 2022
242022
Virtualizing precise event based sampling
MC Merten, BC Strong, MW Chynoweth, GG Zhou, A Kleen, KC Weier, ...
US Patent 9,965,375, 2018
242018
Technologies for allocating resources within a self-managed node
JG Van De Groenendaal, M Ganguli, A Yasin, AJ Herdrich
US Patent 10,567,855, 2020
222020
Technologies for managing the efficiency of workload execution
JG Van De Groenendaal, M Ganguli, A Yasin
US Patent 10,687,127, 2020
202020
A metric-guided method for discovering impactful features and architectural insights for skylake-based processors
A Yasin, J Haj-Yahya, Y Ben-Asher, A Mendelson
ACM Transactions on Architecture and Code Optimization (TACO) 16 (4), 1-25, 2019
192019
A methodology for OLTP micro-architectural analysis
U Sirin, A Yasin, A Ailamaki
Proceedings of the 13th International Workshop on Data Management on New …, 2017
162017
Compiler-directed power management for superscalars
J Haj-Yihia, YB Asher, E Rotem, A Yasin, R Ginosar
ACM Transactions on Architecture and Code Optimization (TACO) 11 (4), 1-21, 2015
162015
Inside 6th gen Intel®Core™: New microarchitecture code named skylake
I Anati, D Blythe, J Doweck, H Jiang, W Kao, J Mandelblat, L Rappoport, ...
2016 IEEE Hot Chips 28 Symposium (HCS), 1-39, 2016
142016
Processor operating by selecting smaller of requested frequency and an energy performance gain (EPG) frequency
Y Aizik, E Weissmann, E Rotem, Y Sabin, D Rajwan, A Yasin
US Patent 9,671,853, 2017
92017
Method and apparatus for processor performance monitoring
MW Chynoweth, JD Combs, AD Schmid, KC Weier, A Yasin, JW Brandt, ...
US Patent 9,465,680, 2016
82016
DOEE: Dynamic optimization framework for better energy efficiency
J Haj-Yihia, A Yasin, Y Ben-Asher
Proceedings of the Symposium on High Performance Computing, 107-114, 2015
82015
How to tune applications using a top-down characterization of microarchitectural issues
J Marusarz, S Cepeda, A Yasin
Technical report, 2013
82013
Performance monitoring in heterogeneous systems
A Yasin, J Mandelblat, E Weissmann, RA Chabukswar, MW Chynoweth
US Patent App. 16/729,370, 2021
62021
Instruction and logic for tracking access to monitored regions
A Yasin, RA Chabukswar, O Levy, MW Chynoweth, CJ Hewett
US Patent 9,626,274, 2017
62017
Causing an interrupt based on event count
A Yasin, PJ Irelan, O Levy, E Ziedan, G Zhou
US Patent 9,575,766, 2017
62017
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