| Modeling of pocket implanted MOSFETs for anomalous analog behavior KM Cao, W Liu, X Jin, K Vashanth, K Green, J Krick, T Vrotsos, C Hu International Electron Devices Meeting 1999. Technical Digest (Cat. No …, 1999 | 103 | 1999 |
| PowerSynth: A power module layout generation tool TM Evans, Q Le, S Mukherjee, I Al Razi, T Vrotsos, Y Peng, HA Mantooth IEEE Transactions on Power Electronics 34 (6), 5063-5078, 2018 | 64 | 2018 |
| Stacked silicon-controlled rectifier having a low voltage trigger and adjustable holding voltage for ESD protection JZ Chen, TA Vrotsos, WT Chen US Patent 6,016,002, 2000 | 54 | 2000 |
| A subthreshold current model for GaAs MESFET's CTM Chang, T Vrotsos, MT Frizzell, R Carroll IEEE electron device letters 8 (2), 69-72, 1987 | 49 | 1987 |
| ESD protection circuit using zener diode and interdigitated NPN transistor JZ Chen, XY Zhang, TA Vrotsos, A Amerasekera US Patent 5,850,095, 1998 | 46 | 1998 |
| Design and layout of a high ESD performance NPN structure for submicron BiCMOS/bipolar circuits JZ Chen, XY Zhang, A Amerasekera, T Vrotsos Proceedings of International Reliability Physics Symposium, 227-232, 1996 | 39 | 1996 |
| Bipolar SCR ESD protection circuit for high speed submicron bipolar/BiCMOS circuits JZ Chen, A Amerasekera, T Vrotsos Proceedings of International Electron Devices Meeting, 337-340, 1995 | 38 | 1995 |
| Bipolar SCR triggering for ESD protection of high speed bipolar/BiCMOS circuits JZ Chen, A Amerasekera, TA Vrotsos US Patent 5,808,342, 1998 | 32 | 1998 |
| Body-triggered ESD protection circuit R Steinhoff, JS Brodsky, TA Vrotsos US Patent 6,424,013, 2002 | 30 | 2002 |
| Tuneable holding voltage SCR ESD protection JZ Chen, TA Vrotsos, YS Chang US Patent 6,172,404, 2001 | 30 | 2001 |
| Adjustable Bipolar SCR holding voltage for ESD protection circuits in high speed Bipolar/BiCMOS circuits JZ Chen, A Amerasekera, TA Vrotsos US Patent 5,747,834, 1998 | 30 | 1998 |
| A Datasheet Driven Unified Si/SiC Compact IGBT Model for N-Channel and P-Channel Devices S Perez, RM Kotecha, AU Rashid, MM Hossain, T Vrotsos, AM Francis, ... IEEE Transactions on Power Electronics 34 (9), 8329-8341, 2018 | 26 | 2018 |
| PNP driven NMOS ESD protection circuit JZ Chen, LB Li, TA Vrotsos, C Duvvury US Patent 5,982,217, 1999 | 23 | 1999 |
| Toward partial discharge reduction by corner correction in power module layouts S Mukherjee, T Evans, B Narayanasamy, Q Le, AI Emon, A Deshpande, ... 2018 IEEE 19th Workshop on Control and Modeling for Power Electronics …, 2018 | 18 | 2018 |
| A physics-based compact device model for GaN HEMT power devices RM Kotecha, Y Zhang, A Rashid, T Vrotsos, HA Mantooth 2016 IEEE 4th Workshop on Wide Bandgap Power Devices and Applications (WiPDA …, 2016 | 16 | 2016 |
| Response surface modeling for parasitic extraction for multi-objective optimization of multi-chip power modules (MCPMs) Q Le, T Evans, S Mukherjee, Y Peng, T Vrotsos, HA Mantooth 2017 IEEE 5th Workshop on Wide Bandgap Power Devices and Applications (WiPDA …, 2017 | 14 | 2017 |
| System and method for electrostatic discharge protection using lateral PNP or PMOS or both for substrate biasing ZJ Chen, TA Vrotsos, EA Amerasekera US Patent 6,628,493, 2003 | 14 | 2003 |
| A physics-based compact gallium nitride power semiconductor device model for advanced power electronics design RM Kotecha, Y Zhang, A Rashid, N Zhu, T Vrotsos, HA Mantooth 2017 IEEE Applied Power Electronics Conference and Exposition (APEC), 2685-2691, 2017 | 12 | 2017 |
| Circuit and method for an integrated charged device model clamp J Brodsky, R Steinhoff, TA Vrotsos US Patent 6,784,496, 2004 | 12 | 2004 |
| DSP & analog SoC integration in the internet era DD Buss, A Chatterjee, TR Efland, B Evans, HD Goodpaster, BS Haroun, ... 2000 IEEE Emerging Technologies Symposium on Broadband, Wireless Internet …, 2000 | 12 | 2000 |
Yarui PengUniversity of ArkansasDirección de correo verificada de uark.edu
