Segueix
Runjie Zhang
Runjie Zhang
EDA, Oracle
Correu electrònic verificat a oracle.com - Pàgina d'inici
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HotSpot 6.0: Validation, Acceleration and Extension
R Zhang, M Stan, K Skadron
University of Virginia, Tech. Rep. CS-2015-04, 2015
1422015
Architecture implications of pads as a scarce resource
R Zhang, K Wang, BH Meyer, MR Stan, K Skadron
ACM SIGARCH Computer Architecture News 42 (3), 373-384, 2014
792014
ArchFP: Rapid prototyping of pre-RTL floorplans
GG Faust, R Zhang, K Skadron, MR Stan, BH Meyer
2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip …, 2012
522012
Some limits of power delivery in the multicore era
R Zhang, BH Meyer, W Huang, K Skadron, MR Stan
Proc. WEED, 1-7, 2012
322012
Walking pads: Fast power-supply pad-placement optimization
K Wang, BH Meyer, R Zhang, K Skadron, M Stan
2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 537-543, 2014
192014
A cross-layer design exploration of charge-recycled power-delivery in many-layer 3D-IC
R Zhang, K Mazumdar, BH Meyer, K Wang, K Skadron, M Stan
Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015
172015
Transient voltage noise in charge-recycled power delivery networks for many-layer 3D-IC
R Zhang, K Mazumdar, BH Meyer, K Wang, K Skadron, MR Stan
2015 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2015
162015
Walking pads: Managing C4 placement for transient voltage noise minimization
K Wang, BH Meyer, R Zhang, MR Stan, K Skadron
Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014
142014
Pre-RTL voltage and power optimization for low-cost, thermally challenged multicore chips
A Roelke, R Zhang, K Mazumdar, K Wang, K Skadron, MR Stan
2017 IEEE International Conference on Computer Design (ICCD), 597-600, 2017
92017
System for placement optimization of chip design for transient noise control and related methods thereof
K Wang, K Skadron, MR Stan, R Zhang
US Patent 10,417,367, 2019
62019
HotSpot 6.0: Validation
R Zhang, MR Stan, K Skadron
Acceleration and Extension, 2017
62017
Tolerating the consequences of multiple em-induced C4 bump failures
R Zhang, BH Meyer, K Wang, MR Stan, K Skadron
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (6 …, 2015
62015
System, method, and computer readable medium for walking pads: fast power-supply pad-placement optimization
K Wang, K Skadron, MR Stan, R Zhang, B Meyer
US Patent 10,482,210, 2019
42019
MTTF enhancement power-C4 bump placement optimization
S Rahimipour, R Zhang, K Wang, K Skadron, FZB Rokhani, MR Stan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (7 …, 2019
32019
Pre-RTL On-Chip Power Delivery Modeling and Analysis
R Zhang
Dept of computer engineering, University of virginia:[date unknown], 2015
32015
Architecture Implications of Pads as a Scarce Resource: Extended Results
R Zhang, K Wang, BH Meyer, MR Stan, K Skadron
University of Virginia, Tech. Rep. CS-2014-01, 2014
32014
ArchFP: rapid prototyping of pre-RTL floorplans. VLSI-SoC
GG Faust, R Zhang, K Skadron, MR Stan, BH Meyer
IEEE, 2012
22012
System for placement optimization of chip design for transient noise control and related methods thereof
K Wang, K Skadron, MR Stan, R Zhang
US Patent 11,436,401, 2022
2022
En aquests moments el sistema no pot dur a terme l'operació. Torneu-ho a provar més tard.
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