Manuel E. Acacio
Manuel E. Acacio
Professor of Computer Science (Universidad de Murcia - SPAIN)
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Owner prediction for accelerating cache-to-cache transfer misses in a cc-NUMA architecture
ME Acacio, J González, JM García, J Duato
SC'02: Proceedings of the 2002 ACM/IEEE Conference on Supercomputing, 49-49, 2002
1012002
A parallel implementation of the 2D wavelet transform using CUDA
J Franco, G Bernabé, J Fernández, ME Acacio
2009 17th Euromicro International Conference on Parallel, Distributed and …, 2009
982009
A two-level directory architecture for highly scalable cc-NUMA multiprocessors
ME Acacio, J Gonzalez, JM Garcia, J Duato
IEEE Transactions on Parallel and Distributed Systems 16 (1), 67-79, 2005
702005
A new scalable directory architecture for large-scale multiprocessors
ME Acacio, J González, JM García, J Duato
Proceedings HPCA Seventh International Symposium on High-Performance …, 2001
652001
The use of prediction for accelerating upgrade misses in cc-NUMA multiprocessors
ME Acacio, J González, JM García, J Duato
Proceedings. International Conference on Parallel Architectures and …, 2002
582002
DiCo-CMP: Efficient cache coherency in tiled CMP architectures
A Ros, ME Acacio, JM García
2008 IEEE International Symposium on Parallel and Distributed Processing, 1-11, 2008
532008
A direct coherence protocol for many-core chip multiprocessors
A Ros, ME Acacio, JM Garcia
IEEE Transactions on Parallel and Distributed Systems 21 (12), 1779-1792, 2010
492010
Heterogeneous interconnects for energy-efficient message management in cmps
A Flores, JL Aragon, ME Acacio
IEEE Transactions on Computers 59 (1), 16-28, 2009
442009
A low overhead fault tolerant coherence protocol for CMP architectures
R Fernández-Pascual, JM Garcia, ME Acacio, J Duato
2007 IEEE 13th International Symposium on High Performance Computer …, 2007
392007
π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory
A Negi, R Titos-Gil, ME Acacio, JM Garcia, P Stenstrom
IEEE International Symposium on High-Performance Comp Architecture, 1-12, 2012
352012
ZEBRA: a data-centric, hybrid-policy hardware transactional memory design
R Titos-Gil, A Negi, ME Acacio, JM García, P Stenstrom
Proceedings of the international conference on Supercomputing, 53-62, 2011
352011
Glocks: Efficient support for highly-contended locks in many-core cmps
JL Abell, J Fern, ME Acacio
2011 IEEE International Parallel & Distributed Processing Symposium, 893-905, 2011
352011
Heterogeneous NoC design for efficient broadcast-based coherence protocol support
M Lodde, J Flich, ME Acacio
2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip, 59-66, 2012
342012
Scalable Directory Organization for Tiled CMP Architectures.
A Ros, ME Acacio, JM García
CDES 8, 112-118, 2008
342008
An architecture for high-performance scalable shared-memory multiprocessors exploiting on-chip integration
ME Acacio, J Gonzalez, JM Garcia, J Duato
IEEE Transactions on Parallel and Distributed Systems 15 (8), 755-768, 2004
312004
Efficient hardware barrier synchronization in many-core cmps
JL Abellán, J Fernandez, ME Acacio
IEEE Transactions on Parallel and Distributed Systems 23 (8), 1453-1466, 2011
272011
Characterizing energy consumption in hardware transactional memory systems
E Gaona-Ramirez, R Titos-Gil, J Fernandez, ME Acacio
2010 22nd International Symposium on Computer Architecture and High …, 2010
242010
An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures
A Flores, JL Aragón, ME Acacio
The Journal of Supercomputing 45 (3), 341-364, 2008
232008
Characterization of conflicts in log-based transactional memory (LogTM)
JRT Gil, MEA Sanchez, JMG Carrasco
16th Euromicro Conference on Parallel, Distributed and Network-Based …, 2008
232008
Ascib: Adaptive selection of cache indexing bits for removing conflict misses
A Ros, P Xekalakis, M Cintra, ME Acacio, JM García
Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012
222012
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Artículos 1–20