| VLSI implementations of threshold logic-a comprehensive survey V Beiu, JM Quintana, MJ Avedillo IEEE Transactions on Neural Networks 14 (5), 1217-1243, 2003 | 306 | 2003 |
| The flywheel leg-curl machine: offering eccentric overload for hamstring development J Tous-Fajardo, RA Maldonado, JM Quintana, M Pozzo, PA Tesch International journal of sports physiology and performance 1 (3), 293, 2006 | 143 | 2006 |
| Low-power CMOS threshold-logic gate MJ Avedillo, JM Quintana, A Rueda, E Jiménez Electronics Letters 31 (25), 2157-2159, 1995 | 63 | 1995 |
| Multi-threshold threshold logic circuit design using resonant tunnelling devices MJ Avedillo, JM Quintana, H Pettenghi, PM Kelly, CJ Thompson Electronics Letters 39 (21), 1, 2003 | 62 | 2003 |
| A threshold logic synthesis tool for RTD circuits MJ Avedillo, JM Quintana Euromicro Symposium on Digital System Design, 2004. DSD 2004., 624-627, 2004 | 50 | 2004 |
| A practical floating-gate Muller-C element using vMOS threshold gates E Rodriguez-Villegas, G Huertas, MJ Avedillo, JM Quintana, A Rueda IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2001 | 48 | 2001 |
| Using multi-threshold threshold gates in RTD-based logic design: A case study H Pettenghi, MJ Avedillo, JM Quintana Microelectronics Journal 39 (2), 241-247, 2008 | 39 | 2008 |
| Increased logic functionality of clocked series-connected RTDs MJ Avedillo, JM Quintana, HP Roldan IEEE Transactions on Nanotechnology 5 (5), 606-611, 2006 | 37 | 2006 |
| State merging and state splitting via state assignment: a new FSM synthesis algorithm MJ Avedillo, JM Quintana, JL Huertas IEE Proceedings-Computers and Digital Techniques 141 (4), 229-237, 1994 | 35 | 1994 |
| Self-latching operation of MOBILE circuits using series-connection of RTDs and transistors MJ Avedillo, JM Quintana, H Pettenghi IEEE Transactions on Circuits and Systems II: Express Briefs 53 (5), 334-338, 2006 | 31 | 2006 |
| Apsidal motion and revised photometric elements of the eccentric eclipsing binary V 477 Cygni A Giménez, JM Quintana Astronomy and Astrophysics (ISSN 0004-6361), vol. 260, no. 1-2, p. 227-236 …, 1992 | 31 | 1992 |
| Oscillatory Neural Networks Using VO2 Based Phase Encoded Logic J Núñez, MJ Avedillo, M Jiménez, JM Quintana, A Todri-Sanial, E Corti, ... Frontiers in Neuroscience 15, 655823, 2021 | 29 | 2021 |
| Synchronisation and chaos in a laser diode driven by a resonant tunnelling diode B Romeira, JML Figueiredo, TJ Slight, L Wang, E Wasige, CN Ironside, ... IET optoelectronics 2 (6), 211-215, 2008 | 25 | 2008 |
| Efficient realisation of MOS-NDR threshold logic gates J Núñez, JM Quintana, MJ Avedillo Institute of Electrical and Electronics Engineers, 2009 | 24 | 2009 |
| Smas: A program for the concurrent state reduction and state assignment of finite state machines MJ Avedillo, JM Quintana, JL Huertas 1991., IEEE International Sympoisum on Circuits and Systems, 1781-1784, 1991 | 24 | 1991 |
| Single phase clock scheme for MOBILE logic gates H Pettenghi, MJ Avedillo, JM Quintana Electronics Letters 42 (24), 1, 2006 | 22 | 2006 |
| Improved nanopipelined RTD adder using generalized threshold gates H Pettenghi, MJ Avedillo, JM Quintana IEEE Transactions on Nanotechnology 10 (1), 155-162, 2009 | 21 | 2009 |
| Practical low-cost CPL implementations threshold logic functions JM Quintana, MJ Avedillo, R Jiménez, E Rodríguez-Villegas Proceedings of the 11th Great Lakes symposium on VLSI, 139-144, 2001 | 21 | 2001 |
| Low-power logic styles for full-adder circuits JM Quintana, MJ Avedillo, R Jiménez, E Rodriguez-Villegas ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and …, 2001 | 18 | 2001 |
| A dynamic model for the state assignment problem M Martinez, MJ Avedillo, JM Quintana, JL Huertas Proceedings Design, Automation and Test in Europe, 835-839, 1998 | 18 | 1998 |
