| Enhancing the static noise margins by upsizing length for ultra-low voltage/power/energy gates M Tache, V Beiu, W Ibrahim, F Kharbash, M Alioto Journal of Low Power Electronics 10 (1), 137-148, 2014 | 11 | 2014 |
| On upsizing length and noise margins V Beiu, M Tache, W Ibrahim, F Kharbash, M Alioto CAS 2013 (International Semiconductor Conference) 2, 219-222, 2013 | 9 | 2013 |
| Reliability and performance of optimised Schmitt trigger gates M Tache, W Ibrahim, F Kharbash, V Beiu The Journal of Engineering 2018 (8), 735-744, 2018 | 8 | 2018 |
| Minimizing communication power using near-neighbor axon-inspired lattices V Beiu, L Zhang, W Ibrahim, M Tache 2011 11th IEEE International Conference on Nanotechnology, 426-430, 2011 | 8 | 2011 |
| On ultra-low power hybrid NEMS-CMOS V Beiu, W Ibrahim, M Tache, TJK Liu 14th IEEE International Conference on Nanotechnology, 201-206, 2014 | 7 | 2014 |
| On axon-inspired communications V Beiu, W Ibrahim, A Beg, L Zhang, M Tache 2011 20th European Conference on Circuit Theory and Design (ECCTD), 789-792, 2011 | 7 | 2011 |
| On sizing transistors for threshold voltage variations V Beiu, W Ibrahim, A Beg, M Tache Proc. DFR, 2012 | 6 | 2012 |
| When one should consider Schmitt trigger gates V Beiu, W Ibrahim, M Tache, F Kharbash 2015 IEEE 15th international conference on nanotechnology (IEEE-NANO), 682-685, 2015 | 5 | 2015 |
| On Schmitt trigger and other inverters W Ibrahim, V Beiu, M Tache, F Kharbash 2013 IEEE 20th International Conference on Electronics, Circuits, and …, 2013 | 5 | 2013 |
| Sizing for static noise margins revisited M Tache, V Beiu, W Ibrahim, F Kharbash, M Alioto Proc. European Workshop on CMOS Variability (VARI'13), Karlsruhe, Germany, 2013 | 5 | 2013 |
| Ultra-low power SRAM cells with unconventional sizing M Al Kaabi, A Al Ali, H Al Janahi, M Al Kendi, M Tache, V Beiu 14th IEEE International Conference on Nanotechnology, 308-313, 2014 | 3 | 2014 |
| Monte Carlo analysis of the static noise margins for CMOS gates in predictive technology models NV Acharya, JL Raju, A Kumar, M Tache, V Beiu 2013 7th IEEE GCC Conference and Exhibition (GCC), 5-10, 2013 | 3 | 2013 |
| Why hybridize NEMS with CMOS? M Tache, V Beiu, TJK Liu 2014 21st IEEE International Conference on Electronics, Circuits and Systems …, 2014 | 2 | 2014 |
| Reliability enhanced SRAM bit-cells V Beiu, M Tache, F Kharbash 2014 International Semiconductor Conference (CAS), 229-232, 2014 | 2 | 2014 |
| Using body bias when upsizing length for maximizing the static noise margins of CMOS gates F Kharbash, V Beiu, M Tache, W Ibrahim 2013 IEEE 20th International Conference on Electronics, Circuits, and …, 2013 | 2 | 2013 |
| On using Schmitt trigger for digital logic V Beiu, M Tache 2015 International Semiconductor Conference (CAS), 197-200, 2015 | 1 | 2015 |
| Statistical analysis of static noise margins V Beiu, M Tache 2015 European Conference on Circuit Theory and Design (ECCTD), 1-4, 2015 | 1 | 2015 |
| On SRAM bit-cells once again M Tache, F Kharbash, V Beiu 2014 10th International Conference on Innovations in Information Technology …, 2014 | 1 | 2014 |
| Green AI from Kirchhoff to Shannon M Tache, SH Hoară, VF Drăgoi, V Beiu International Conference on Computers Communications and Control, 433-443, 2022 | | 2022 |
| On Threshold Voltage Variation-Tolerant Designs V Beiu, M Tache Theory and Applications of Mathematics & Computer Science 7 (1), 47-58, 2017 | | 2017 |
