Nacho Navarro
TitleCited byYear
An asymmetric distributed shared memory model for heterogeneous parallel systems
I Gelado, JE Stone, J Cabezas, S Patel, N Navarro, WW Hwu
ACM SIGARCH Computer Architecture News 38 (1), 347-358, 2010
Decomposable and responsive power models for multicore processors using performance counters
R Bertran, M Gonzalez, X Martorell, N Navarro, E Ayguade
Proceedings of the 24th ACM International Conference on Supercomputing, 147-158, 2010
Predictive runtime code scheduling for heterogeneous architectures
VJ Jiménez, L Vilanova, I Gelado, M Gil, G Fursin, N Navarro
International Conference on High-Performance Embedded Architectures and …, 2009
Enabling preemptive multiprogramming on GPUs
I Tanasic, I Gelado, J Cabezas, A Ramirez, N Navarro, M Valero
2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA …, 2014
Didi: Mitigating the performance impact of tlb shootdowns using a shared tlb directory
C Villavieja, V Karakostas, L Vilanova, Y Etsion, A Ramirez, A Mendelson, ...
2011 International Conference on Parallel Architectures and Compilation …, 2011
Thread fork/join techniques for multi-level parallelism exploitation in NUMA multiprocessors
X Martorell, E Ayguadé, N Navarro, J Corbalán, M González, J Labarta
International Conference on Supercomputing: Proceedings of the 13 th …, 1999
Implicitly parallel programming models for thousand-core microprocessors
W Hwu, S Ryoo, SZ Ueng, JH Kelm, I Gelado, SS Stone, RE Kidd, ...
Proceedings of the 44th annual Design Automation Conference, 754-759, 2007
Assessing accelerator-based HPC reverse time migration
M Araya-Polo, J Cabezas, M Hanzich, M Pericas, F Rubio, I Gelado, ...
IEEE Transactions on Parallel and Distributed Systems 22 (1), 147-162, 2010
High-performance embedded architecture and compilation roadmap
K De Bosschere, W Luk, X Martorell, N Navarro, M O’Boyle, ...
Transactions on High-Performance Embedded Architectures and Compilers I, 5-29, 2007
Beating in-order stalls with" flea-flicker" two-pass pipelining
RD Barnes, JW Sias, EM Nystrom, SJ Patel, J Navarro, WW Hwu
IEEE Transactions on Computers 55 (1), 18-33, 2005
TERAFLUX: Harnessing dataflow in next generation teradevices
R Giorgi, RM Badia, F Bodin, A Cohen, P Evripidou, P Faraboschi, ...
Microprocessors and Microsystems 38 (8), 976-990, 2014
A library implementation of the nano-threads programming model
X Martorell, J Labarta, N Navarro, E Ayguadé
European Conference on Parallel Processing, 644-649, 1996
A systematic methodology to generate decomposable and responsive power models for CMPs
R Bertran, M Gonzalez, X Martorell, N Navarro, E Ayguade
IEEE Transactions on Computers 62 (7), 1289-1302, 2012
NANOSCompiler: A research platform for OpenMP extensions
E Ayguade, M Gonzalez, J Labarta, X Martorell, N Navarro, J Oliver
in the First EuropeanWorkshop on OpenMP, 1999
The hipeac vision
M Duranton, S Yehia, B De Sutter, K De Bosschere, A Cohen, B Falsafi, ...
Report, European Network of Excellence on High Performance and Embedded …, 2010
Exploiting multiple levels of parallelism in openmp: A case study
E Ayguade, X Martorell, J Labarta, M Gonzalez, N Navarro
Proceedings of the 1999 International Conference on Parallel Processing, 172-180, 1999
Energy accounting for shared virtualized environments under DVFS using PMC-based power models
R Bertran, Y Becerra, D Carrera, V Beltran, M Gonzàlez, X Martorell, ...
Future Generation Computer Systems 28 (2), 457-468, 2012
DITools: Application-level Support for Dynamic Extension and Flexible Composition.
A Serra, N Navarro, T Cortes
USENIX Annual Technical Conference, General Track, 225-238, 2000
NanosCompiler: supporting flexible multilevel parallelism exploitation in OpenMP
M Gonzalez, E Ayguadé, X Martorell, J Labarta, N Navarro, J Oliver
Concurrency: Practice and Experience 12 (12), 1205-1218, 2000
The HiPEAC Vision 2019
M Duranton, K De Bosschere, B Coppens, C Gamrat, M Gray, H Munk, ...
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Articles 1–20