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Jorge Juan
Jorge Juan
Profesor Titular de Universidad, Universidad de Sevilla, España
Verified email at dte.us.es - Homepage
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Cited by
Cited by
Year
Logical modelling of delay degradation effect in static CMOS gates
MJ Bellido-Diaz, J Juan-Chico, AJ Acosta, M Valencia, JL Huertas
IEE Proceedings-Circuits, Devices and Systems 147 (2), 107-117, 2000
862000
Python as a hardware description language: A case study
JI Villar, J Juan, MJ Bellido, J Viejo, D Guerrero, J Decaluwe
2011 VII Southern Conference on Programmable Logic (SPL), 117-122, 2011
352011
Logic-timing simulation and the degradation delay model
MJ Bellido, JJ Chico, M Valencia
Imperial College Press, 2005
302005
Inertial and degradation delay model for CMOS logic gates
J Juan-Chico, PR de Clavijo, MJ Bellido, AJ Acosta, M Valenia
2000 IEEE International Symposium on Circuits and Systems (ISCAS) 1, 459-462, 2000
242000
Degradation delay model extension to CMOS gates
J Juan-Chico, MJ Bellido, P Ruiz-de-Clavijo, AJ Acosta, M Valencia
International Workshop on Power and Timing Modeling, Optimization and …, 2000
232000
Halotis: High accuracy logic timing simulator with inertial and degradation delay model
PR de Clavijo Vazquez, J Juan-Chico, MJ Bellido, A Acosta, M Valencia
Proceedings Design, Automation and Test in Europe. Conference and Exhibition …, 2001
192001
Characterization of normal propagation delay for delay degradation model (DDM)
A Millán, J Juan, MJ Bellido, P Ruiz-de-Clavijo, D Guerrero
International Workshop on Power and Timing Modeling, Optimization and …, 2002
162002
Measurement of the switching activity of CMOS digital circuits at the gate level
C Baena, J Juan-Chico, MJ Bellido, P Clavijo, CJ Jimenez, M Valencia
International Workshop on Power and Timing Modeling, Optimization and …, 2002
162002
Analysis of metastable operation in a CMOS dynamic D-latch
J Juan-Chico, MJ Bellido, AJ Acosta, M Valencia, JL Huertas
Analog Integrated Circuits and Signal Processing 14 (1), 143-157, 1997
151997
Delay degradation effect in submicronic CMOS inverters
J Juan Chico, MJ Bellido Díaz, AJ Acosta Jiménez, Á Barriga Barros, ...
PATMOS 1997: 6th International Workshop on Power and Timing Modeling …, 1997
151997
Un ejemplo de implemetación de una distribución Linux en un SoC basado en hardware Linux
A Muñoz, E Ostúa, P Ruiz, MJ Bellido, J Viejo, A Millan, J Juan, ...
Actas de las IV jornadas de computación reconfigurable y aplicaciones (JCRA …, 2007
142007
Building a SoC for industrial applications based on LEON microprocessor and a GNU/Linux distribution
A Muñoz, E Ostua, MJ Bellido, A Millan, J Juan, D Guerrero
2008 IEEE International Symposium on Industrial Electronics, 1727-1732, 2008
132008
Design and implementation of a SNTP client on FPGA
J Viejo, J Juan, MJ Bellido, E Ostua, A Millan, P Ruiz-de-Clavijo, A Munoz, ...
2008 IEEE International Symposium on Industrial Electronics, 1971-1975, 2008
112008
Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements.
J Viejo, MJ Bellido, A Millán, E Ostúa, J Juan, P Ruiz-de-Clavijo, ...
IES, 1-7, 2006
112006
Digital data processing peripheral design for an embedded application based on the microblaze soft core
E Ostua, J Viejo, MJ Bellido, A Millan, J Juan, A Munoz
2008 4th Southern Conference on Programmable Logic, 197-200, 2008
102008
Simulation-driven switching activity evaluation of CMOS digital circuits
C Baena, J Juan, MJ Bellido, P Ruiz-de Clavijo, CJ Jimenez, M Valencia
Proc. 16th Conference on Design of Circuits and Integrated Systems (DCIS), 2001
92001
AUTODDM: AUTOmatic characterization tool for the Delay Degradation Model
J Juan-Chico, MJ Bellido, P Ruiz-de-Clavijo, C Baena, M Valencia
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and …, 2001
92001
Influence of clocking strategies on the design of low switching-noise digital and mixed-signal VLSI circuits
AJ Acosta, R Jiménez, J Juan, MJ Bellido, M Valencia
International Workshop on Power and Timing Modeling, Optimization and …, 2000
92000
Diseno eficiente de un modulo FFT/IFFT sobre FPGA
A Millan, MJ Bellido, J Juan, P Ruiz-de Clavijo, D Guerrero, E Ostua
Proc. III Reconfigurable Computing and Applications Conference (JCRA), 107-114, 2003
82003
Internode: Internal node logic computational model
A Millan, MJ Bellido, J Juan, D Guerrero, P Ruiz-de-Clavijo, E Ostua
36th Annual Simulation Symposium, 2003., 241-248, 2003
82003
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