Guido Masera

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Maurizio MartinaDipartimento di Elettronica e Telecomunicazioni, Politecnico di TorinoDirección de correo verificada de polito.it
Ashfaq AhmedKhalifa University, Abu Dhabi, UAEDirección de correo verificada de ku.ac.ae
E. BoutillonLab-STICC, Université de Bretagne SudDirección de correo verificada de univ-ubs.fr
Emanuele ViterboMonash UniversityDirección de correo verificada de monash.edu
Luca FanucciProfessor of Electronics, Pisa University, PisaDirección de correo verificada de unipi.it
Sergio Saponara. Full ProfessorDepartment of Information Engineering, University of PisaDirección de correo verificada de iet.unipi.it
Luca AmarùPrincipal R&D Engineer at Synopsys Inc.Dirección de correo verificada de synopsys.com
Marco GrangettoFull Professor, Università di TorinoDirección de correo verificada de unito.it
Paolo GiacconeAssociate Professor, Politecnico di Torino, Department of Electronics and Telecommunications, ItalyDirección de correo verificada de polito.it
Enrico MagliProfessore Ordinario, Politecnico di TorinoDirección de correo verificada de polito.it
Andrea BiancoPolitecnico di Torino - Department of Electronics and TelecommunicationsDirección de correo verificada de polito.it
Patrick RobertsonGoogle Inc.Dirección de correo verificada de google.com
Abdullah AtalarProfessor of Electrical Engineering at Bilkent University (Ankara, TURKEY)Dirección de correo verificada de bilkent.edu.tr
Christophe MoyProfessor, Université de Rennes 1, IETR - CNRS UMR 6164, FranceDirección de correo verificada de univ-rennes1.fr
Matteo SONZA REORDAPolitecnico di Torino, Dept. of Control and Computer EngineeringDirección de correo verificada de polito.it
Marco Ajmone MarsanIMDEA Networks Institute, SpainDirección de correo verificada de imdea.org
Ismael Gomez-MiguelezSoftware Radio Systems LimitedDirección de correo verificada de softwareradiosystems.com
Silvano PupolinProfessor of Telecommunications, University of PaduaDirección de correo verificada de dei.unipd.it
olivier mullerAssociate professor of computer science, Grenoble Institut of Technology, Ensimag/TIMA SLSDirección de correo verificada de imag.fr
Sergio PalazzoProfessor, University of Catania, ItalyDirección de correo verificada de dieei.unict.it

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Guido Masera

Professor of Electronics, Politecnico di Torino

Dirección de correo verificada de polito.it

digital integrated circuits


Título Ordenar por citas Ordenar por año Ordenar por título	Citado por Citado por	Año
VLSI architectures for turbo codes G Masera, G Piccinini, MR Roch, M Zamboni IEEE Transactions on Very Large Scale Integration (VLSI) Systems 7 (3), 369-379, 1999	216	1999
Implementation of a flexible LDPC decoder G Masera, F Quaglio, F Vacca IEEE Transactions on Circuits and Systems II: Express Briefs 54 (6), 542-546, 2007	165	2007
An updated survey of efficient hardware architectures for accelerating deep convolutional neural networks M Capra, B Bussolino, A Marchisio, M Shafique, G Masera, M Martina Future Internet 12 (7), 113, 2020	147	2020
Hardware and software optimizations for accelerating deep neural networks: Survey of current trends, challenges, and the road ahead M Capra, B Bussolino, A Marchisio, G Masera, M Martina, M Shafique IEEE Access 8, 225134-225180, 2020	130	2020
Edge computing: A survey on the hardware requirements in the internet of things world M Capra, R Peloso, G Masera, M Ruo Roch, M Martina Future Internet 11 (4), 100, 2019	117	2019
Multiplierless, folded 9/7–5/3 wavelet VLSI architecture M Martina, G Masera IEEE Transactions on Circuits and Systems II: Express Briefs 54 (9), 770-774, 2007	93	2007
VLSI implementation of a multi-mode turbo/LDPC decoder architecture C Condo, M Martina, G Masera IEEE Transactions on Circuits and Systems I: Regular Papers 60 (6), 1441-1454, 2012	76	2012
Architectural strategies for low-power VLSI turbo decoders G Masera, M Mazza, G Piccinini, F Viglione, M Zamboni IEEE Transactions on Very Large Scale Integration (VLSI) Systems 10 (3), 279-285, 2002	69	2002
High speed architectures for finding the first two maximum/minimum values LG Amaru, M Martina, G Masera IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20 (12 …, 2011	65	2011
Low-complexity, efficient 9/7 wavelet filters VLSI implementation M Martina, G Masera IEEE Transactions on Circuits and Systems II: Express Briefs 53 (11), 1289-1293, 2006	63	2006
A VLSI architecture for IWT (integer wavelet transform) M Martina, G Masera, G Piccinini, M Zamboni Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat …, 2000	59	2000
On optimal and near-optimal turbo decoding using generalized max operator S Papaharalabos, PT Mathiopoulos, G Masera, M Martina IEEE Communications Letters 13 (7), 522-524, 2009	57	2009
Quantum dot cellular automata check node implementation for LDPC decoders M Awais, M Vacca, M Graziano, MR Roch, G Masera IEEE transactions on nanotechnology 12 (3), 368-377, 2013	55	2013
Adaptive approximated DCT architectures for HEVC M Masera, M Martina, G Masera IEEE Transactions on Circuits and Systems for Video Technology 27 (12), 2714 …, 2016	51	2016
Finite precision implementation of LDPC decoders G Masera, F Quaglio, F Vacca IEE Proceedings-Communications 152 (6), 1098-1102, 2005	48	2005
Motion estimation and CABAC VLSI co-processors for real-time high-quality H. 264/AVC video coding S Saponara, M Martina, M Casula, L Fanucci, G Masera Microprocessors and Microsystems 34 (7-8), 316-328, 2010	45	2010
Turbo NOC: A framework for the design of network-on-chip-based turbo decoder architectures M Martina, G Masera IEEE Transactions on Circuits and Systems I: Regular Papers 57 (10), 2776-2789, 2010	44	2010
A flexible UMTS-WiMax turbo decoder architecture M Martina, M Nicola, G Masera IEEE Transactions on Circuits and Systems II: Express Briefs 55 (4), 369-373, 2008	43	2008
Interconnection framework for high-throughput, flexible LDPC decoders F Quaglio, F Vacca, C Castellano, A Tarable, G Masera Proceedings of the Design Automation & Test in Europe Conference 2, 6 pp., 2006	36	2006
Carsnn: An efficient spiking neural network for event-based autonomous cars on the loihi neuromorphic research processor A Viale, A Marchisio, M Martina, G Masera, M Shafique 2021 International Joint Conference on Neural Networks (IJCNN), 1-10, 2021	31	2021

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