Upset hardened memory design for submicron CMOS technology T Calin, M Nicolaidis, R Velazco
IEEE Transactions on nuclear science 43 (6), 2874-2878, 1996
1590 1996 A survey on fault injection techniques H Ziade, RA Ayoubi, R Velazco
Int. Arab J. Inf. Technol. 1 (2), 171-186, 2004
421 2004 Radiation effects on embedded systems R Velazco, P Fouillat, R Reis
Springer Science & Business Media, 2007
203 2007 Predicting error rate for microprocessor-based digital architectures through CEU (Code Emulating Upsets) injection R Velazco, S Rezgui, R Ecoffet
IEEE Transactions on Nuclear Science 47 (6), 2405-2411, 2000
184 2000 Experimentally evaluating an automatic approach for generating safety-critical software with respect to transient errors P Cheynet, B Nicolescu, R Velazco, M Rebaudengo, MS Reorda, ...
IEEE Transactions on Nuclear Science 47 (6), 2231-2236, 2000
151 2000 Two CMOS memory cells suitable for the design of SEU-tolerant VLSI circuits R Velazco, D Bessot, S Duzellier, R Ecoffet, R Koga
IEEE Transactions on Nuclear Science 41 (6), 2229-2234, 1994
131 1994 Detecting soft errors by a purely software approach: method, tools and experimental results B Nicolescu, R Velazco
Embedded Software for SoC, 39-51, 2003
126 2003 Design of SEU-hardened CMOS memory cells: the HIT cell D Bessot, R Velazco
RADECS 93. Second European Conference on Radiation and its Effects on …, 1993
117 1993 Software detection mechanisms providing full coverage against single bit-flip faults B Nicolescu, Y Savaria, R Velazco
IEEE Transactions on Nuclear science 51 (6), 3510-3518, 2004
93 2004 An automated SEU fault-injection method and tool for HDL-based designs W Mansour, R Velazco
IEEE Transactions on Nuclear Science 60 (4), 2728-2733, 2013
89 2013 Assessing contact graph routing performance and reliability in distributed satellite constellations JA Fraire, P Madoery, S Burleigh, M Feldmann, J Finochietto, A Charif, ...
Journal of Computer Networks and Communications 2017 (1), 2830542, 2017
83 2017 Deep submicron CMOS technologies for the LHC experiments P Jarron, G Anelli, T Calin, J Cosculluela, M Campbell, M Delmastro, ...
Nuclear Physics B-Proceedings Supplements 78 (1-3), 625-634, 1999
79 1999 Single event effects in static and dynamic registers in a 0.25/spl mu/m CMOS technology F Faccio, K Kloukinas, A Marchioro, T Calin, J Cosculluela, M Nicolaidis, ...
IEEE Transactions on Nuclear Science 46 (6), 1434-1439, 1999
77 1999 Total dose and single event effects (SEE) in a F Faccio, R Velazco, T Calin, A Marchioro, KC Kloukinas, W Snoeys, ...
73 1999 SEU-hardened storage cell validation using a pulsed laser R Velazco, T Calin, M Nicolaidis, SC Moss, SD LaLumondiere, VT Tran, ...
IEEE Transactions on Nuclear Science 43 (6), 2843-2848, 1996
68 1996 SEU induced errors observed in microprocessor systems V Asenek, C Underwood, R Velazco, S Rezgui, M Oldfield, P Cheynet, ...
IEEE Transactions on Nuclear Science 45 (6), 2876-2883, 1998
60 1998 THESIC: A testbed suitable for the qualification of integrated circuits devoted to operate in harsh environment R Velazco, P Cheynet, A Bofill, R Ecoffet
IEEE European Test Workshop (ETW'98), 1998
57 1998 Combining results of accelerated radiation tests and fault injections to predict the error rate of an application implemented in SRAM-based FPGAs R Velazco, G Foucard, P Peronnard
IEEE Transactions on Nuclear Science 57 (6), 3500-3505, 2010
55 2010 Estimating error rates in processor-based architectures S Rezgui, R Velazco, R Ecoffet, S Rodriguez, JR Mingo
IEEE Transactions on Nuclear Science 48 (5), 1680-1687, 2001
55 2001 SIED: Software implemented error detection B Nicolescu, Y Savaria, R Velazco
Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI …, 2003
54 2003 