| A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1/spl mu/m/sup 2/SRAM cell S Thompson, N Anand, M Armstrong, C Auth, B Arcot, M Alavi, P Bai, ... Digest. International Electron Devices Meeting,, 61-64, 2002 | 452 | 2002 |
| A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57/spl mu/m/sup 2/SRAM cell P Bai, C Auth, S Balakrishnan, M Bost, R Brain, V Chikarmane, ... IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004 | 382 | 2004 |
| A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects S Tyagi, M Alavi, R Bigwood, T Bramblett, J Brandenburg, W Chen, ... International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No …, 2000 | 179 | 2000 |
| 130nm Logic Technology Featuring 60nm Transistors, Low-K Dielectrics, and Cu Interconnects. S Thompson, M Alavi, M Hussein, P Jacob, C Kenyon, P Moon, M Prince, ... Intel Technology Journal 6 (2), 2002 | 111 | 2002 |
| A high performance 180 nm generation logic technology S Yang, S Ahmed, B Arcot, R Arghavani, P Bai, S Chambers, P Charvat, ... International Electron Devices Meeting 1998. Technical Digest (Cat. No …, 1998 | 111 | 1998 |
| IEDM Tech. Dig. S Thompson, N Anand, M Armstrong, C Auth, B Arcot, M Alavi, P Bai, ... IEDM Tech. Dig, 61, 2002 | 99 | 2002 |
| An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7-1.4 V S Thompson, M Alavi, R Arghavani, A Brand, R Bigwood, J Brandenburg, ... International Electron Devices Meeting. Technical Digest (Cat. No. 01CH37224 …, 2001 | 94 | 2001 |
| Method of making a transistor having a deposited dual-layer spacer structure LN Brigham, RE Cotner, MA Hussein US Patent 5,714,413, 1998 | 89 | 1998 |
| Materials' impact on interconnect process technology and reliability MA Hussein, J He IEEE Transactions on Semiconductor Manufacturing 18 (1), 69-85, 2005 | 88 | 2005 |
| Interconnect structures containing conductive electrolessly deposited etch stop layers, liner layers, and via plugs VM Dubin, CC Cheng, M Hussein, PL Nguyen, RA Brain US Patent 6,958,547, 2005 | 83 | 2005 |
| Method for patterning dual damascene interconnects using a sacrificial light absorbing material MA Hussein, S Sivakumar US Patent 6,365,529, 2002 | 75 | 2002 |
| Method for patterning dual damascene interconnects using a sacrificial light absorbing material MA Hussein, S Sivakumar US Patent 6,329,118, 2001 | 71 | 2001 |
| Use of conductive electrolessly deposited etch stop layers, liner layers and via plugs in interconnect structures VM Dubin, CC Cheng, M Hussein, PL Nguyen, RA Brain US Patent 7,008,872, 2006 | 64 | 2006 |
| Thermoelectric cooling for microelectronic packages and dice GM Chrysler, PA Koning, S Jayaraman, MA Hussein US Patent 6,981,380, 2006 | 57 | 2006 |
| Process to manufacture continuous metal interconnects MA Hussein US Patent 6,169,024, 2001 | 56 | 2001 |
| Modeling of plasma flow downstream of an electron cyclotron resonance plasma source MA Hussein, GA Emmert Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films 8 (3 …, 1990 | 49 | 1990 |
| Pattern-sensitive deposition for damascene processing MA Hussein, AM Myers, CH Recchia, S Sivakumar, AW Kandas US Patent 6,406,995, 2002 | 47 | 2002 |
| Method of forming an air gap intermetal layer dielectric (ILD) by utilizing a dielectric material to bridge underlying metal lines MA Hussein, P Moon, J Powers, KP O'brien US Patent 6,908,829, 2005 | 41 | 2005 |
| Method for making integrated circuit having polymer interlayer dielectric MA Hussein, S Sivakumar, R Davis US Patent 6,037,255, 2000 | 41 | 2000 |
| Effect of collisions on ion dynamics in electron‐cyclotron‐resonance plasmas MA Hussein, GA Emmert, N Hershkowitz, R Claude Woods Journal of applied physics 72 (5), 1720-1728, 1992 | 39 | 1992 |
Boyan BoyanovIlluminaVerified email at illumina.com
