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Vinicius Callegaro
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Graph-based transistor network generation method for supergate design
VN Possani, V Callegaro, AI Reis, RP Ribas, F de Souza Marques, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (2), 692-705, 2015
412015
Factored forms for memristive material implication stateful logic
FS Marranghello, V Callegaro, MGA Martins, AI Reis, RP Ribas
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 5 (2 …, 2015
262015
KL-cut based digital circuit remapping
L Machado, M Martins, V Callegaro, RP Ribas, AI Reis
NORCHIP 2012, 1-4, 2012
222012
A simple and effective heuristic method for threshold logic identification
A Neutzling, MGA Martins, V Callegaro, AI Reis, RP Ribas
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
212017
SwitchCraft: a framework for transistor network design
V Callegaro, FS Marques, CE Klock, LS da Rosa Jr, RP Ribas, AI Reis
Proceedings of the 23rd symposium on Integrated circuits and system design …, 2010
202010
SOP based logic synthesis for memristive IMPLY stateful logic
FS Marranghello, V Callegaro, AI Reis, RP Ribas
2015 33rd IEEE International Conference on Computer Design (ICCD), 228-235, 2015
152015
Functional composition paradigm and applications
MGA Martins, V Callegaro, L Machado, RP Ribas, AI Reis
International Workshop on Logic and Synthesis (IWLS’2012). Berkeley, CA, 2012
132012
Four-level forms for memristive material implication logic
FS Marranghello, V Callegaro, AI Reis, RP Ribas
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (5 …, 2019
122019
Majority-based logic synthesis for nanometric technologies
MGA Martins, V Callegaro, FS Marranghello, RP Ribas, AI Reis
14th IEEE International Conference on Nanotechnology, 256-261, 2014
122014
Efficient method to compute minimum decision chains of Boolean functions
MGA Martins, V Callegaro, RP Ribas, AI Reis
Proceedings of the 21st edition of the great lakes symposium on Great lakes …, 2011
122011
Improved Logic Synthesis for Memristive Stateful Logic Using Multi-Memristor Implication
FS MARRANGHELLO, V Callegaro, MGA MARTINS, AI REIS, RP Ribas
South Symposium on Microelectronics, 2015
112015
Iterative remapping respecting timing constraints
L Machado, MGA Martins, V Callegaro, RP Ribas, AI Reis
2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 236-241, 2013
102013
Read-Polarity-Once Functions
V CALLEGARO, MGA MARTINS, RP RIBAS, AI REIS
International Workshop on Logic & Synthesis, 2012
10*2012
Bottom-up disjoint-support decomposition based on cofactor and boolean difference analysis
V Callegaro, FS Marranghello, MGA Martins, RP Ribas, AI Reis
2015 33rd IEEE International Conference on Computer Design (ICCD), 680-687, 2015
92015
Contributions to the evaluation of ensembles of combinational logic gates
RP Ribas, S Bavaresco, N Schuch, V Callegaro, M Lubaszewski, AI Reis
Microelectronics Journal 42 (2), 371-381, 2011
92011
Read-polarity-once Boolean functions
V Callegaro, MGA Martins, RP Ribas, AI Reis
2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2013
72013
Improving the methodology to build non-series-parallel transistor arrangements
VN Possani, V Callegaro, AI Reis, RP Ribas, FS Marques, LS da Rosa
2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2013
72013
NSP kernel finder-A methodology to find and to build non-series-parallel transistor arrangements
VN Possani, FS Marques, LS da Rosa Junior, V Callegaro, AI Reis, ...
2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2012
62012
Circuit Design for Testing Standard Cell Libraries
RP Ribas, V Callegaro, M Lubaszewski, A Ivanov, AI Reis
Workshop on Circuits and Systems Design, 2011
42011
Computing Minimum Decision Chains of Boolean Functions
MGA Martins, V Callegaro, RP Ribas, AI Reis
South Symposium on Microelectronics, 2011
42011
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Articles 1–20