| VTR 7.0: Next generation architecture and CAD system for FPGAs J Luu, J Goeders, M Wainberg, A Somerville, T Yu, K Nasartschuk, M Nasr, ... ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7 (2), 1-30, 2014 | 354 | 2014 |
| The VTR project: architecture and CAD for FPGAs from verilog to routing J Rose, J Luu, CW Yu, O Densmore, J Goeders, A Somerville, KB Kent, ... Proceedings of the ACM/SIGDA international symposium on Field Programmable …, 2012 | 321 | 2012 |
| Effective FPGA debug for high-level synthesis generated circuits J Goeders, SJE Wilton 2014 24th International Conference on Field Programmable Logic and …, 2014 | 56 | 2014 |
| VersaPower: Power estimation for diverse FPGA architectures JB Goeders, SJE Wilton 2012 International Conference on Field-Programmable Technology, 229-234, 2012 | 52 | 2012 |
| Using dynamic signal-tracing to debug compiler-optimized HLS circuits on FPGAs J Goeders, SJE Wilton 2015 IEEE 23rd annual international symposium on field-programmable custom …, 2015 | 47 | 2015 |
| Signal-tracing techniques for in-system FPGA debugging of high-level synthesis circuits J Goeders, SJE Wilton IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016 | 43 | 2016 |
| Deterministic timing-driven parallel placement by simulated annealing using half-box window decomposition JB Goeders, GGF Lemieux, SJE Wilton 2011 International Conference on Reconfigurable Computing and FPGAs, 41-48, 2011 | 21 | 2011 |
| Legup high-level synthesis A Canis, J Choi, B Fort, B Syrowik, RL Lian, YT Chen, H Hsiao, J Goeders, ... FPGAs for Software Programmers, 175-190, 2016 | 15 | 2016 |
| Microcontroller compiler-assisted software fault tolerance M Bohman, B James, MJ Wirthlin, H Quinn, J Goeders IEEE Transactions on Nuclear Science 66 (1), 223-232, 2018 | 12 | 2018 |
| Architecture exploration for HLS-Oriented FPGA debug overlays AS Jamal, J Goeders, SJE Wilton Proceedings of the 2018 ACM/SIGDA International Symposium on Field …, 2018 | 12 | 2018 |
| Allowing software developers to debug HLS hardware J Goeders, SJE Wilton arXiv preprint arXiv:1508.06805, 2015 | 12 | 2015 |
| An FPGA overlay architecture supporting rapid implementation of functional changes during on-chip debug AS Jamal, J Goeders, SJE Wilton 2018 28th International Conference on Field Programmable Logic and …, 2018 | 8 | 2018 |
| Using round-robin tracepoints to debug multithreaded hls circuits on fpgas J Goeders, SJE Wilton 2015 International Conference on Field Programmable Technology (FPT), 40-47, 2015 | 8 | 2015 |
| Accelerating in-system FPGA debug of high-level synthesis circuits using incremental compilation techniques PK Bussa, J Goeders, SJE Wilton 2017 27th International Conference on Field Programmable Logic and …, 2017 | 7 | 2017 |
| Faster FPGA debug: Efficiently coupling trace instruments with user circuitry E Hung, JB Goeders, SJE Wilton International Symposium on Applied Reconfigurable Computing, 73-84, 2014 | 7 | 2014 |
| Demand driven assembly of fpga configurations using partial reconfiguration, ubuntu linux, and pynq J Goeders, T Gaskin, B Hutchings 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom …, 2018 | 5 | 2018 |
| Applying compiler-automated software fault tolerance to multiple processor platforms B James, H Quinn, M Wirthlin, J Goeders IEEE Transactions on Nuclear Science 67 (1), 321-327, 2019 | 4 | 2019 |
| An overlay for rapid fpga debug of machine learning applications DH Noronha, R Zhao, Z Que, J Goeders, W Luk, S Wilton 2019 International Conference on Field-Programmable Technology (ICFPT), 135-143, 2019 | 4 | 2019 |
| Power aware architecture exploration for field programmable gate arrays JB Goeders, SJE Wilton Journal of Low Power Electronics 10 (3), 297-312, 2014 | 4 | 2014 |
| Fast Turnaround HLS Debugging Using Dependency Analysis and Debug Overlays AS Jamal, E Cahill, J Goeders, SJE Wilton ACM Transactions on Reconfigurable Technology and Systems (TRETS) 13 (1), 1-26, 2020 | 3 | 2020 |
