Jeffrey Goeders
Title
Cited by
Cited by
Year
VTR 7.0: Next generation architecture and CAD system for FPGAs
J Luu, J Goeders, M Wainberg, A Somerville, T Yu, K Nasartschuk, M Nasr, ...
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7 (2), 1-30, 2014
3312014
The VTR project: architecture and CAD for FPGAs from verilog to routing
J Rose, J Luu, CW Yu, O Densmore, J Goeders, A Somerville, KB Kent, ...
Proceedings of the ACM/SIGDA international symposium on Field Programmable …, 2012
3022012
Effective FPGA debug for high-level synthesis generated circuits
J Goeders, SJE Wilton
2014 24th International Conference on Field Programmable Logic and …, 2014
522014
Using dynamic signal-tracing to debug compiler-optimized HLS circuits on FPGAs
J Goeders, SJE Wilton
2015 IEEE 23rd annual international symposium on field-programmable custom …, 2015
472015
VersaPower: Power estimation for diverse FPGA architectures
JB Goeders, SJE Wilton
2012 International Conference on Field-Programmable Technology, 229-234, 2012
442012
Signal-tracing techniques for in-system FPGA debugging of high-level synthesis circuits
J Goeders, SJE Wilton
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016
352016
Deterministic timing-driven parallel placement by simulated annealing using half-box window decomposition
JB Goeders, GGF Lemieux, SJE Wilton
2011 International Conference on Reconfigurable Computing and FPGAs, 41-48, 2011
192011
LegUp high-level synthesis
A Canis, J Choi, B Fort, B Syrowik, RL Lian, YT Chen, H Hsiao, J Goeders, ...
FPGAs for Software Programmers, 175-190, 2016
142016
Allowing software developers to debug HLS hardware
J Goeders, SJE Wilton
arXiv preprint arXiv:1508.06805, 2015
122015
Architecture exploration for HLS-Oriented FPGA debug overlays
AS Jamal, J Goeders, SJE Wilton
Proceedings of the 2018 ACM/SIGDA International Symposium on Field …, 2018
112018
Using round-Robin tracepoints to debug multithreaded HLS circuits on FPGAs
J Goeders, SJE Wilton
2015 International Conference on Field Programmable Technology (FPT), 40-47, 2015
82015
Accelerating in-system FPGA debug of high-level synthesis circuits using incremental compilation techniques
PK Bussa, J Goeders, SJE Wilton
2017 27th International Conference on Field Programmable Logic and …, 2017
72017
Faster FPGA debug: Efficiently coupling trace instruments with user circuitry
E Hung, JB Goeders, SJE Wilton
International Symposium on Applied Reconfigurable Computing, 73-84, 2014
72014
Microcontroller compiler-assisted software fault tolerance
M Bohman, B James, MJ Wirthlin, H Quinn, J Goeders
IEEE Transactions on Nuclear Science 66 (1), 223-232, 2018
62018
An FPGA overlay architecture supporting rapid implementation of functional changes during on-chip debug
AS Jamal, J Goeders, SJE Wilton
2018 28th International Conference on Field Programmable Logic and …, 2018
62018
Demand Driven Assembly of FPGA Configurations Using Partial Reconfiguration, Ubuntu Linux, and PYNQ
J Goeders, T Gaskin, B Hutchings
2018 IEEE 26th Annual International Symposium on Field-Programmable Custom …, 2018
42018
Power aware architecture exploration for field programmable gate arrays
JB Goeders, SJE Wilton
Journal of Low Power Electronics 10 (3), 297-312, 2014
42014
Unified on-chip software and hardware debug for hls-accelerated programs
MB Ashcraft, J Goeders
2018 International Conference on Field-Programmable Technology (FPT), 354-357, 2018
32018
Quantifying observability for in-system debug of high-level synthesis circuits
J Goeders, SJE Wilton
2016 26th International Conference on Field Programmable Logic and …, 2016
32016
Fast Turnaround HLS Debugging Using Dependency Analysis and Debug Overlays
AS Jamal, E Cahill, J Goeders, SJE Wilton
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 13 (1), 1-26, 2020
12020
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