Ignacio Herrera-Alzu, PhD
Ignacio Herrera-Alzu, PhD
Dirección de correo verificada de die.upm.es
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Año
Design Techniques for Xilinx Virtex FPGA Configuration Memory Scrubbers
I Herrera-Alzu, M López-Vallejo
IEEE, 2013
912013
Design techniques for Xilinx Virtex FPGA configuration memory scrubbers
I Herrera-Alzu, M Lopez-Vallejo
IEEE transactions on Nuclear Science 60 (1), 376-385, 2013
912013
System design framework and methodology for Xilinx Virtex FPGA configuration scrubbers
I Herrera-Alzu, M Lopez-Vallejo
IEEE Transactions on Nuclear Science 61 (1), 619-629, 2014
192014
System design framework and methodology for Xilinx Virtex FPGA configuration scrubbers
I Herrera-Alzu, M Lopez-Vallejo
IEEE Transactions on Nuclear Science 61 (1), 619-629, 2014
192014
Self-reference scrubber for TMR systems based on xilinx virtex FPGAs
I Herrera-Alzu, M López-Vallejo
International Workshop on Power and Timing Modeling, Optimization and …, 2011
132011
Experimental methodology for power characterization of FPGAs
I Herrera-Alzu, MA Sanchez, M López-Vallejo, P Echeverria
2008 15th IEEE International Conference on Electronics, Circuits and Systems …, 2008
72008
Cycle-accurate configuration layer model for Xilinx Virtex FPGAs
I Herrera-Alzu, M López-Vallejo
Radiation and Its Effects on Components and Systems (RADECS), 2011 12th …, 2011
52011
Integrated oscillator circuit with a memory based frequency control circuit and associated methods
IH Alzu, R Peon, M Visee, RW Walden
US Patent 6,271,733, 2001
52001
A Dual-Layer Fault Manager for systems based on Xilinx Virtex FPGAs
I Herrera-Alzu, M López-Vallejo, CG Soriano
2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2015
2015
Fault management techniques for systems with SRAM-based FPGAs
I Herrera Alzu
Telecomunicacion, 2015
2015
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