Mohit Ganeriwala
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Modeling of Quantum Confinement and Capacitance in III–V Gate-All-Around 1-D Transistors
MD Ganeriwala, C Yadav, FG Ruiz, EG Marin, YS Chauhan, ...
IEEE Transactions on Electron Devices 64 (12), 4889-4896, 2017
92017
Modeling of charge and quantum capacitance in low effective mass III-V FinFETs
MD Ganeriwala, C Yadav, NR Mohapatra, S Khandelwal, C Hu, ...
IEEE Journal of the Electron Devices Society 4 (6), 396-401, 2016
82016
A compact charge and surface potential model for III–V cylindrical nanowire transistors
MD Ganeriwala, FG Ruiz, EG Marin, NR Mohapatra
IEEE Transactions on Electron Devices 66 (1), 73-79, 2018
62018
Anomalous Width Dependence of Gate Current in High- Metal Gate nMOS Transistors
P Duhan, MD Ganeriwala, VR Rao, NR Mohapatra
IEEE Electron Device Letters 36 (8), 739-741, 2015
52015
Compact Modeling of Gate Capacitance in III–V Channel Quadruple-Gate FETs
C Yadav, MD Ganeriwala, NR Mohapatra, A Agarwal, YS Chauhan
IEEE Transactions on Nanotechnology 16 (4), 703-710, 2017
42017
Computationally efficient analytic charge model for III-V cylindrical nanowire transistors
MD Ganeriwala, EG Marin, FG Ruiz, NR Mohapatra
2018 Joint International EUROSOI Workshop and International Conference on …, 2018
22018
An Unified Charge Centroid Model for Silicon and Low Effective Mass III-V Channel Double Gate MOS Transistors
A Gupta, M Ganeriwala, NR Mohapatra
2019 32nd International Conference on VLSI Design and 2019 18th …, 2019
12019
Effect of Pregate Carbon Implant on Narrow Width Behavior and Performance of High- Metal-Gate nMOS Transistors
NR Mohapatra, MD Ganeriwala
IEEE Transactions on Electron Devices 63 (7), 2708-2713, 2016
12016
Significance of L-valley charges and a method to include it in electrostatic model of III-V GAA FETs
MD Ganeriwala, FG Ruiz, EG Marin, NR Mohapatra
2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 1-4, 2020
2020
A compact model for III–V nanowire electrostatics including band non-parabolicity
MD Ganeriwala, FG Ruiz, EG Marin, NR Mohapatra
Journal of Computational Electronics, 2019
2019
Capacitance and Surface Potential Model for III-V Double-Gate FET
SC GM, MD Ganeriwala, NR Mohapatra
2019 2nd International Symposium on Devices, Circuits and Systems (ISDCS), 1-5, 2019
2019
Charge and Capacitance Compact Model for III-V Quadruple-Gate FETs With Square Geometry
MD Ganeriwala, EG Marin, FG Ruiz, NR Mohapatra
2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK …, 2019
2019
A Simple Charge and Capacitance Compact Model for Asymmetric III-V DGFETs using CCDA
MD Ganeriwala, SGM GM, NR Mohapatra
4th IEEE International Conference on Emerging Electronics, Bangalore, 2018, 2018
2018
Analysis of Gate Leakage Current in High-k Metal Gate MOS Transistors
MD Ganeriwala
Indian Institute of Technology, Ganadhinagar, 2015
2015
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Artículos 1–14