| Effective SAT-based solutions for generating functional sequences maximizing the sustained switching activity in a pipelined processor NI Deligiannis, R Cantoro, T Faller, T Paxian, B Becker, MS Reorda 2021 IEEE 30th Asian Test Symposium (ATS), 73-78, 2021 | 10 | 2021 |
| Towards SAT-based SBST generation for RISC-V cores T Faller, P Scholl, T Paxian, B Becker 2021 IEEE 22nd Latin American Test Symposium (LATS), 1-2, 2021 | 6 | 2021 |
| Constraint-based automatic SBST generation for RISC-V processor families T Faller, NI Deligiannis, M Schwörer, MS Reorda, B Becker 2023 IEEE European Test Symposium (ETS), 1-6, 2023 | 4 | 2023 |
| Automating the generation of programs maximizing the repeatable constant switching activity in microprocessor units via MaxSAT NI Deligiannis, T Faller, R Cantoro, T Paxian, B Becker, MS Reorda IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023 | 4 | 2023 |
| A survey of recent developments in testability, safety and security of risc-v processors J Anders, P Andreu, B Becker, S Becker, R Cantoro, NI Deligiannis, ... 2023 IEEE European Test Symposium (ETS), 1-10, 2023 | 1 | 2023 |
| Automating the Generation of Functional Stress Inducing Stimuli for Burn-In Testing NI Deligiannis, T Faller, Z Chenghan, R Cantoro, B Becker, MS Reorda 2023 IEEE European Test Symposium (ETS), 1-5, 2023 | 1 | 2023 |
| Automatic Identification of Functionally Untestable Cell-Aware Faults in Microprocessors NI Deligiannis, T Faller, I Guglielminetti, R Cantoro, B Becker, MS Reorda 2023 IEEE 32nd Asian Test Symposium (ATS), 1-6, 2023 | | 2023 |
| Scale4Edge-Scaling RISC-V for Edge Applications W Ecker, M Krstic, M Ulbricht, A Mauderer, E Jentzsch, A Koch, ... | | 2023 |
| Using Formal Methods to Support the Development of STLs for GPUs NI Deligiannis, T Faller, JER Condia, R Cantoro, B Becker, MS Reorda 2022 IEEE 31st Asian Test Symposium (ATS), 84-89, 2022 | | 2022 |
