| An hybrid eDRAM/SRAM macrocell to implement first-level data caches A Valero, J Sahuquillo, S Petit, V Lorente, R Canal, P López, J Duato Proceedings of the 42nd Annual IEEE/ACM International Symposium on …, 2009 | 46 | 2009 |
| Design, performance, and energy consumption of eDRAM/SRAM macrocells for L1 data caches A Valero, S Petit, J Sahuquillo, P López, J Duato IEEE Transactions on Computers 61 (9), 1231-1242, 2012 | 22 | 2012 |
| Design of Hybrid Second-Level Caches A Valero, J Sahuquillo, S Petit, P Lopez, J Duato IEEE Transactions on Computers 64 (7), 1884-1897, 2015 | 21 | 2015 |
| On Microarchitectural Mechanisms for Cache Wearout Reduction A Valero, N Miralaei, S Petit, J Sahuquillo, T Jones IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (3), 857-871, 2017 | 18 | 2017 |
| Combining recency of information with selective random and a victim cache in last-level caches A Valero, J Sahuquillo, S Petit, P López, J Duato ACM Transactions on Architecture and Code Optimization (TACO) 9 (3), 1-20, 2012 | 16 | 2012 |
| An Aging-Aware GPU Register File Design Based on Data Redundancy A Valero, F Candel, D Suárez-Gracia, S Petit, J Sahuquillo IEEE Transactions on Computers 68 (1), 4-20, 2019 | 9 | 2019 |
| Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes V Lorente, A Valero, J Sahuquillo, S Petit, R Canal, P López, J Duato 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 83-88, 2013 | 9 | 2013 |
| Analyzing the optimal ratio of SRAM banks in hybrid caches A Valero, J Sahuquillo, S Petit, P López, J Duato 2012 IEEE 30th International Conference on Computer Design (ICCD), 297-302, 2012 | 9 | 2012 |
| Impact on performance and energy of the retention time and processor frequency in L1 macrocell-based data caches A Valero, J Sahuquillo, V Lorente, S Petit, P Lopez, J Duato IEEE transactions on very large scale integration (VLSI) systems 20 (6 …, 2012 | 7 | 2012 |
| A reuse-based refresh policy for energy-aware eDRAM caches A Valero, S Petit, J Sahuquillo, DR Kaeli, J Duato Microprocessors and Microsystems 39 (1), 37-48, 2015 | 6 | 2015 |
| MRU-tour-based replacement algorithms for last-level caches A Valero, J Sahuquillo, S Petit, P López, J Duato 2011 23rd International Symposium on Computer Architecture and High …, 2011 | 6 | 2011 |
| Enhancing the L1 Data Cache Design to Mitigate HCI A Valero, N Miralaei, S Petit, J Sahuquillo, T Jones IEEE Computer Architecture Letters 15 (2), 93-96, 2016 | 4 | 2016 |
| Exploiting reuse information to reduce refresh energy in on-chip eDRAM caches A Valero, J Sahuquillo, S Petit, J Duato Proceedings of the 27th International ACM Conference on Supercomputing, 491-492, 2013 | 4 | 2013 |
| Improving GPU Cache Hierarchy Performance with a Fetch and Replacement Cache F Candel, S Petit, A Valero, J Sahuquillo Proceedings of the 24th International European Conference on Parallel and …, 2018 | 3 | 2018 |
| Improving Last-Level Cache Performance by Exploiting the Concept of MRU-Tour A Valero, J Sahuquillo, S Petit, P López, J Duato 2011 International Conference on Parallel Architectures and Compilation …, 2011 | 3 | 2011 |
| Exposing Abstraction-Level Interactions with a Parallel Ray Tracer A Valero, D Suárez Gracia, R Gran Tejero, LM Ramos, A Navarro-Torres, ... Proceedings of the Workshop on Computer Architecture Education, 5:1-5:8, 2019 | 2 | 2019 |
| Exploiting Data Compression to Mitigate Aging in GPU Register Files F Candel, A Valero, S Petit, D Suárez-Gracia, J Sahuquillo Computer Architecture and High Performance Computing (SBAC-PAD), 2017 29th …, 2017 | 2 | 2017 |
| A learning experience toward the understanding of abstraction-level interactions in parallel applications A Valero, R Gran-Tejero, D Suárez-Gracia, EA Georgescu, J Ezpeleta, ... Journal of Parallel and Distributed Computing 156, 38-52, 2021 | 1 | 2021 |
| DC-Patch: A Microarchitectural Fault Patching Technique for GPU Register Files A Valero, D Suárez-Gracia, R Gran-Tejero IEEE Access 8, 173276-173288, 2020 | 1 | 2020 |
| Atomicidad, Consistencia, Paralelismo y Concurrencia en un Trazador de Rayos elaborado a lo largo del Grado en Ingenierıa Informatica A Valero, DS Gracia, R Gran, A Munoz, J Ezpeleta, JL Briz, LM Ramos, ... XXIX Jornadas de Paralelismo, 2018 | 1 | 2018 |
Julio SahuquilloProfessor, Universitat Politecnica de Valencia, SpainVerified email at disca.upv.es
