| BTI, HCI and TDDB aging impact in flip–flops C Nunes, PF Butzen, AI Reis, RP Ribas Microelectronics Reliability 53 (9), 1355-1359, 2013 | 44 | 2013 |
| A methodology to evaluate the aging impact on flip-flops performance C Nunes, PF Butzen, AI Reis, RP Ribas Integrated Circuits and Systems Design (SBCCI), 2013 26th Symposium on, 1-6, 2013 | 6 | 2013 |
| Standard Cell Library Validation Methodology M de Carvalho, C Nunes, B Canal, L Puricelli, L Reinicke, G Webber | 2* | |
| Avaliação de Famílias Lógicas para Circuitos com Baixo Consumo de Potência CS Nunes, R Grande Monograf, 0 | 2* | |
| CTC06 Standard Cell Library Design C Nunes, L Puricelli, LH Reinicke, M Altieri, B Canal, M Erigson, ... Workshop Circuits and Systems, 2016 | | 2016 |
| MCML Gate Design for Standard Cell Library B Canal, CS Nunes, RP Ribas, EE Fabris Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 3, 2015 | | 2015 |
| MCML Standard Cell Library: topologies analysis B Canal, CS Nunes, RP Ribas, EE Fabris | | |
| Aging Effects Analysis in Flip-Flops C Nunes, PF Butzen, AI Reis, RP Ribas | | |
| ENERGY EVALUATION OF NANOMETER CMOS TECHNOLOGIES C Nunes, C Meinhardt, PF Butzen | | |
| Evaluating the Efficacy of Low Power Process to Design Low Power Circuits CS Nunes, AN Silva, IAC Gomes, C Meinhardth | | |
