Jie-Hong Roland Jiang
Jie-Hong Roland Jiang
Professor of Electrical Engineering, National Taiwan University
Dirección de correo verificada de ntu.edu.tw
TítuloCitado porAño
FRAIGs: A unifying representation for logic synthesis and verification
A Mishchenko, S Chatterjee, R Jiang, RK Brayton
ERL Technical Report, 2005
Unified QBF certification and its applications
V Balabanov, JHR Jiang
Formal Methods in System Design 41 (1), 45-65, 2012
Scalable don't-care-based logic optimization and resynthesis
A Mishchenko, R Brayton, JHR Jiang, S Jang
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 4 (4), 34, 2011
Scalable exploration of functional dependency by interpolation and incremental SAT solving
CC Lee, JHR Jiang, CYR Huang, A Mishchenko
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided …, 2007
M Gao, JH Jiang, Y Jiang, Y Li, S Sinha, R Brayton
Proc. of the Intl. Workshop on Logic Synthesis, 2001
QBF resolution systems and their proof complexities
V Balabanov, M Widl, JHR Jiang
International Conference on Theory and Applications of Satisfiability …, 2014
Bi-decomposing large Boolean functions via interpolation and satisfiability solving
RR Lee, JHR Jiang, WL Hung
2008 45th ACM/IEEE Design Automation Conference, 636-641, 2008
Interpolating functions from large Boolean relations
JHR Jiang, HP Lin, WL Hung
2009 IEEE/ACM International Conference on Computer-Aided Design-Digest of …, 2009
Optimization of multi-valued multi-level networks
M Gao, JH Jiang, Y Jiang, Y Li, A Mishchenko, S Sinha, T Villa, R Brayton
Proceedings 32nd IEEE International Symposium on Multiple-Valued Logic, 168-177, 2002
Retiming and resynthesis: A complexity perspective
JHR Jiang, RK Brayton
IEEE transactions on computer-aided design of integrated circuits and …, 2006
On the verification of sequential equivalence
JHR Jiang, RK Brayton
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2003
Henkin quantifiers and Boolean formulae: A certification perspective of DQBF
V Balabanov, HJK Chiang, JHR Jiang
Theoretical Computer Science 523, 86-100, 2014
SAT-based logic optimization and resynthesis
RK Brayton, JHR Jiang, S Jang
Proc. of International Workshop on Logic Synthesis, 358-364, 2007
Resolution proofs and Skolem functions in QBF evaluation and applications
V Balabanov, JHR Jiang
International Conference on Computer Aided Verification, 149-164, 2011
A robust functional ECO engine by SAT proof minimization and interpolation techniques
BH Wu, CJ Yang, CYR Huang, JHR Jiang
Proceedings of the International Conference on Computer-Aided Design, 729-734, 2010
To SAT or not to SAT: Ashenhurst decomposition in a large scale
HP Lin, JHR Jiang, RR Lee
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided …, 2008
Functional dependency for verification reduction
JHR Jiang, RK Brayton
International Conference on Computer Aided Verification, 268-280, 2004
Efficient extraction of QBF (counter) models from long-distance resolution proofs
V Balabanov, JHR Jiang, M Janota, M Widl
Twenty-Ninth AAAI Conference on Artificial Intelligence, 2015
To SAT or not to SAT: Scalable exploration of functional dependency
JHR Jiang, CC Lee, A Mishchenko, CY Huang
IEEE Transactions on Computers 59 (4), 457-467, 2010
Compatible class encoding in hyper-function decomposition for FPGA synthesis
JHR Jiang, JY Jou, JY Jou, JY Jou, JD Huang
Proceedings of the 35th annual Design Automation Conference, 712-717, 1998
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