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Hideharu Amano
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A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface
N Miura, Y Koizumi, E Sasaki, Y Take, H Matsutani, T Kuroda, H Amano, ...
2013 IEEE COOL Chips XVI, 1-3, 2013
1872013
A case for random shortcut topologies for HPC interconnects
M Koibuchi, H Matsutani, H Amano, DF Hsu, H Casanova
ACM Sigarch Computer Architecture News 40 (3), 177-188, 2012
1862012
A lightweight fault-tolerant mechanism for network-on-chip
M Koibuchi, H Matsutani, H Amano, TM Pinkston
Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), 13-22, 2008
1802008
WASMII: A data driven computer on a virtual hardware
XP Ling, H Amano
[1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines, 33-42, 1993
1481993
Recursive diagonal torus: an interconnection network for massively parallel computers
Y Yang, A Funahashi, A Jouraku, H Nishi, H Amano, T Sueyoshi
IEEE Transactions on Parallel and Distributed Systems 12 (7), 701-715, 2001
145*2001
Prediction router: Yet another low latency on-chip router architecture
H Matsutani, M Koibuchi, H Amano, T Yoshinaga
2009 IEEE 15th International Symposium on High Performance Computer …, 2009
1352009
Run-time power gating of on-chip routers using look-ahead routing
H Matsutani, M Koibuchi, H Amano, D Wang
2008 Asia and South Pacific Design Automation Conference, 55-60, 2008
1312008
Extracting success from ibm’s 20-qubit machines using error-aware compilation
S Nishio, Y Pan, T Satoh, H Amano, RV Meter
ACM Journal on Emerging Technologies in Computing Systems (JETC) 16 (3), 1-25, 2020
1222020
Ultra fine-grained run-time power gating of on-chip routers for CMPs
H Matsutani, M Koibuchi, D Ikebuchi, K Usami, H Nakamura, H Amano
2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip, 61-68, 2010
122*2010
A survey on dynamically reconfigurable processors
H Amano
IEICE transactions on Communications 89 (12), 3179-3187, 2006
1132006
Pulmonary lesions associated with Sjogren's syndrome: radiographic and CT findings
N Matsuyama, K Ashizawa, T Okimoto, J Kadota, H Amano, K Hayashi
The British journal of radiology 76 (912), 880-884, 2003
1042003
Tightly-coupled multi-layer topologies for 3-D NoCs
H Matsutani, M Koibuchi, H Amano
2007 International Conference on Parallel Processing (ICPP 2007), 75-75, 2007
1002007
WASMII: An MPLD with data-driven control on a virtual hardware
X Ling, H Amano
The Journal of supercomputing 9, 253-276, 1995
901995
Cool mega-arrays: Ultralow-power reconfigurable accelerator chips
N Ozaki, Y Yasuda, M Izawa, Y Saito, D Ikebuchi, H Amano, H Nakamura, ...
IEEE Micro 31 (6), 6-18, 2011
832011
A scalable 3D heterogeneous multicore with an inductive ThruChip interface
N Miura, Y Koizumi, Y Take, H Matsutani, T Kuroda, H Amano, ...
IEEE Micro 33 (6), 6-15, 2013
78*2013
3D NoC with inductive-coupling links for building-block SiPs
Y Take, H Matsutani, D Sasaki, M Koibuchi, T Kuroda, H Amano
IEEE Transactions on Computers 63 (3), 748-763, 2012
782012
L-turn routing: An adaptive routing in irregular networks
M Koibuchi, A Funahashi, A Jouraku, H Amano
International Conference on Parallel Processing, 2001., 383-392, 2001
772001
A fine-grain dynamic sleep control scheme in MIPS R3000
N Seki, L Zhao, J Kei, D Ikebuchi, Y Kojima, Y Hasegawa, H Amano, ...
2008 IEEE International Conference on Computer Design, 612-617, 2008
762008
Adding slow-silent virtual channels for low-power on-chip networks
H Matsutani, M Koibuchi, D Wang, H Amano
Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), 23-32, 2008
752008
A case for wireless 3D NoCs for CMPs
H Matsutani, P Bogdan, R Marculescu, Y Take, D Sasaki, H Zhang, ...
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 23-28, 2013
71*2013
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