| Tiny but mighty: designing and realizing scalable latency tolerance for manycore socs M Orenes-Vera, A Manocha, J Balkind, F Gao, JL Aragón, D Wentzlaff, ... Proceedings of the 49th Annual International Symposium on Computer …, 2022 | 16 | 2022 |
| MosaicSim: A lightweight, modular simulator for heterogeneous systems O Matthews, A Manocha, D Giri, M Orenes-Vera, E Tureci, T Sorensen, ... 2020 IEEE International Symposium on Performance Analysis of Systems and …, 2020 | 16 | 2020 |
| Dalorex: A data-local program execution and architecture for memory-bound applications M Orenes-Vera, E Tureci, D Wentzlaff, M Martonosi 2023 IEEE International Symposium on High-Performance Computer Architecture …, 2023 | 13 | 2023 |
| Using LLMs to Facilitate Formal Verification of RTL M Orenes-Vera, M Martonosi, D Wentzlaff arXiv e-prints, arXiv: 2309.09437, 2023 | 10* | 2023 |
| AutoSVA: Democratizing Formal Verification of RTL Module Interactions M Orenes-Vera, A Manocha, D Wentzlaff, M Martonosi 58th ACM/IEEE Design Automation Conference, DAC 2021 2021, 6, 2021 | 10 | 2021 |
| Cohort: Software-oriented acceleration for heterogeneous socs T Wei, N Turtayeva, M Orenes-Vera, O Lonkar, J Balkind Proceedings of the 28th ACM International Conference on Architectural …, 2023 | 8 | 2023 |
| A simulator and compiler framework for agile hardware-software co-design evaluation and exploration T Sorensen, A Manocha, E Tureci, M Orenes-Vera, JL Aragón, ... Proceedings of the 39th International Conference on Computer-Aided Design, 1-9, 2020 | 7 | 2020 |
| DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including … F Gao, TJ Chang, A Li, M Orenes-Vera, D Giri, PJ Jackson, A Ning, ... 2023 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2023 | 4 | 2023 |
| Wafer-scale fast fourier transforms M Orenes-Vera, I Sharapov, R Schreiber, M Jacquelin, P Vandermersch, ... Proceedings of the 37th International Conference on Supercomputing, 180-191, 2023 | 3 | 2023 |
| Massive data-centric parallelism in the chiplet era M Orenes-Vera, E Tureci, D Wentzlaf, M Martonosi arXiv preprint arXiv:2304.09389, 2023 | 3 | 2023 |
| AutoCC: Automatic Discovery of Covert Channels in Time-Shared Hardware M Orenes-Vera, H Yun, N Wistoff, G Heiser, L Benini, D Wentzlaff, ... Proceedings of the 56th Annual IEEE/ACM International Symposium on …, 2023 | 2 | 2023 |
| CIFER: A Cache-Coherent 12nm 16mm 2 SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm 2 Synthesizable eFPGA A Li, TJ Chang, F Gao, T Ta, G Tziantzioulis, Y Ou, M Wang, J Tu, K Xu, ... IEEE Solid-State Circuits Letters, 2023 | 2 | 2023 |
| CIFER: A 12nm, 16mm2, 22-Core SoC with a 1541 LUT6/mm2 1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA TJ Chang, A Li, F Gao, T Ta, G Tziantzioulis, Y Ou, M Wang, J Tu, K Xu, ... 2023 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2023 | 2 | 2023 |
| RECITE: A framework for user trajectory analysis in cultural sites M Orenes-Vera, F Terroso-Saenz, M Valdes-Vela Journal of Ambient Intelligence and Smart Environments 13 (5), 389-409, 2021 | 2 | 2021 |
| Muchisim: A Simulation Framework for Design Exploration of Multi-Chip Manycore Systems M Orenes-Vera, E Tureci, M Martonosi, D Wentzlaff arXiv preprint arXiv:2312.10244, 2023 | 1 | 2023 |
| Tascade: Hardware support for atomic-free, asynchronous and efficient reduction trees M Orenes-Vera, E Tureci, D Wentzlaff, M Martonosi arXiv preprint arXiv:2311.15810, 2023 | 1 | 2023 |
| DCRA: A distributed chiplet-based reconfigurable architecture for irregular applications M Orenes-Vera, E Tureci, M Martonosi, D Wentzlaff arXiv preprint arXiv:2311.15443, 2023 | 1 | 2023 |
| The MosaicSim Simulator (Full Technical Report) O Matthews, A Manocha, D Giri, M Orenes-Vera, E Tureci, T Sorensen, ... arXiv preprint arXiv:2004.07415, 2020 | 1 | 2020 |
| Data Processing Systems A Garcia-Guirado, M Orenes-Vera US Patent US11169806B1, 2021 | | 2021 |
Margaret MartonosiProfessor of Computer Science, Princeton UniversityVerified email at princeton.edu
