| Method for fabricating semiconductor devices with reduced junction diffusion B Colombeau, SH Yeong, F Benistant, B Indajang, L Chan US Patent 8,053,340, 2011 | 102 | 2011 |
| Method for fabricating semiconductor devices with reduced junction diffusion B Colombeau, SH Yeong, F Benistant, B Indajang, L Chan US Patent 8,354,321, 2013 | 94 | 2013 |
| Strain relaxation in transistor channels with embedded epitaxial silicon germanium source/drain JP Liu, K Li, SM Pandey, FL Benistant, A See, MS Zhou, LC Hsia, ... Applied Physics Letters 93 (22), 2008 | 42 | 2008 |
| Comprehensive model of damage accumulation in silicon KRC Mok, F Benistant, M Jaraiz, JE Rubio, P Castrillo, R Pinacho, ... Journal of Applied Physics 103 (1), 2008 | 37 | 2008 |
| Re-examination of indium implantation for a low power 0.1/spl mu/m technology P Bouillon, F Benistant, T Skotnicki, G Guegan, D Roche, E Andre, ... Proceedings of International Electron Devices Meeting, 897-900, 1995 | 35 | 1995 |
| Isolation scheme for high voltage device K Liu, F Benistant, M Li, MUN Namchil, SY Ong, PR Verma US Patent 9,673,084, 2017 | 27 | 2017 |
| Device with diffusion blocking layer in source/drain region SM Pandey, P Zhao, ZHU Baofu, FL Benistant US Patent 9,947,788, 2018 | 23 | 2018 |
| Mechanism of stress memorization technique (SMT) and method to maximize its effect SM Pandey, J Liu, ZS Hooi, S Flachowsky, T Herrmann, W Tao, ... IEEE electron device letters 32 (4), 467-469, 2011 | 23 | 2011 |
| A novel CMOS compatible L-shaped impact-ionization MOS (LI-MOS) transistor EH Toh, GH Wang, GQ Lo, N Balasubramanian, CH Tung, F Benistant, ... IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest …, 2005 | 20 | 2005 |
| Extended drain metal-oxide-semiconductor transistor K Liu, X Wang, FL Benistant, L Cao US Patent 9,871,132, 2018 | 19 | 2018 |
| The impact of nitrogen co-implantation on boron ultra-shallow junction formation and underlying physical understanding SH Yeong, B Colombeau, KRC Mok, F Benistant, CJ Liu, ATS Wee, ... Materials Science and Engineering: B 154, 43-48, 2008 | 18 | 2008 |
| Novel stress-free keep out zone process development for via middle TSV in 20nm planar CMOS technology MA Rabie, CS Premachandran, R Ranjan, MI Natarajan, SF Yap, D Smith, ... IEEE International Interconnect Technology Conference, 203-206, 2014 | 17 | 2014 |
| Understanding of carbon/fluorine co-implant effect on boron-doped junction formed during soak annealing SH Yeong, B Colombeau, KRC Mok, F Benistant, CJ Liu, ATS Wee, ... Journal of The Electrochemical Society 155 (2), H69, 2007 | 15 | 2007 |
| Dual floating gate programmable read only memory cell structure and method for its fabrication and operation F Gonzalez, FL Benistant US Patent 6,649,470, 2003 | 15 | 2003 |
| First-principles investigations of TiGe/Ge interface and recipes to reduce the contact resistance H Dixit, C Niu, M Raymond, V Kamineni, RK Pandey, A Konar, ... IEEE Transactions on Electron Devices 64 (9), 3775-3780, 2017 | 14 | 2017 |
| Influence of stress induced CT local layout effect (LLE) on 14nm FinFET P Zhao, SM Pandey, E Banghart, X He, R Asra, V Mahajan, H Zhang, ... 2017 Symposium on VLSI Technology, T228-T229, 2017 | 14 | 2017 |
| Dual floating gate programmable read only memory cell structure and method for its fabrication and operation F Gonzalez, FL Benistant US Patent 6,492,228, 2002 | 14 | 2002 |
| A heavy ion implanted pocket 0.10 μm n‐type metal–oxide–semiconductor field effect transistor with hybrid lithography (electron‐beam/deep ultraviolet) and … F Benistant, S Tedesco, G Guegan, F Martin, M Heitzmann, B Dal’zotto Journal of Vacuum Science & Technology B: Microelectronics and Nanometer …, 1996 | 13 | 1996 |
| 38.3 A Novel CMOS-Compatible L-Shaped Impact-Ionization MOS (LI-MOS) Transistor EH Toh, GH Wang, GQ Lo, N Balasubramanian, CH Tung, F Benistant, ... INTERNATIONAL ELECTRON DEVICES MEETING 1 (1), 971-974, 2003 | 12 | 2003 |
| Extraction of parasitic and channel resistance components in FinFETs using TCAD tools S Narayanan, E Banghart, P Zeitzoff, K Korablev, SM Pandey, ... Solid-State Electronics 123, 44-50, 2016 | 11 | 2016 |
Sai Hooi (Allen), YeongIntegrated Materials Solutions (IMS), Applied MaterialsVerified email at amat.com
