Josep L. Rossello
Josep L. Rossello
Associate Professor, Physics Dept. Universitat de les Illes Balears, Spain
Verified email at uib.es
TitleCited byYear
An analytical charge-based compact delay model for submicrometer CMOS inverters
JL Rosselló, J Segura
IEEE Transactions on Circuits and Systems I: Regular Papers 51 (7), 1301-1311, 2004
562004
A new stochastic computing methodology for efficient neural network implementation
V Canals, A Morro, A Oliver, ML Alomar, JL Rosselló
IEEE Transactions on Neural Networks and Learning Systems 27 (3), 551-564, 2016
542016
A variable threshold voltage inverter for CMOS programmable logic circuits
J Segura, JL Rossello, J Morra, H Sigg
IEEE Journal of Solid-State Circuits 33 (8), 1262-1265, 1998
531998
Studying the role of synchronized and chaotic spiking neural ensembles in neural information processing
JL Rossello, V Canals, A Oliver, A Morro
International journal of neural systems 24 (05), 1430003, 2014
462014
Charge-based analytical model for the evaluation of power consumption in submicron CMOS buffers
JL Rosselló, J Segura
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2002
462002
Hardware implementation of stochastic spiking neural networks
JL Rossello, V Canals, A Morro, A Oliver
International journal of neural systems 22 (04), 1250014, 2012
372012
Chaos-based mixed signal implementation of spiking neurons
JL Rossello, V Canals, A Morro, J Verd
International Journal of Neural Systems 19 (06), 465-471, 2009
342009
Impact of thermal gradients on clock skew and testing
SA Bota, JL Rossello, C De Benito, A Keshavarzi, J Segura
IEEE Design & Test of Computers 23 (5), 414-424, 2006
292006
A compact gate-level energy and delay model of dynamic CMOS gates
JL Rosselló, C de Benito, J Segura
IEEE Transactions on Circuits and Systems II: Express Briefs 52 (10), 685-689, 2005
262005
Ultra-fast data-mining hardware architecture based on stochastic computing
A Morro, V Canals, A Oliver, ML Alomar, JL Rossello
PloS one 10 (5), 2015
252015
A simple CMOS chaotic integrated circuit
JL Rosselló, V Canals, I De Paul, S Bota, A Morro
IEICE Electronics Express 5 (24), 1042-1048, 2008
232008
Smart temperature sensor for thermal testing of cell-based ICs
SA Bota, M Rosales, JL Rosselló, J Segura
Design, Automation and Test in Europe, 464-465, 2005
222005
Within die thermal gradient impact on clock-skew: a new type of delay-fault mechanism
S Bota, M Rosales, JL Rosselló, J Segura
International Test Conference 2004, 2004
222004
Transient current testing based on current (charge) integration
I De Paul, R Picos, JL Rossello, M Roca, E Isern, J Segura, CF Hawkins
Proceedings 1998 IEEE International Workshop on IDDQ Testing (Cat. No …, 1998
221998
FPGA-based stochastic echo state networks for time-series forecasting
ML Alomar, V Canals, N Perez-Mora, V Martínez-Moll, JL Rosselló
Computational intelligence and neuroscience 2016, 2016
212016
A Stochastic Spiking Neural Network for Virtual Screening
A Morro, V Canals, A Oliver, ML Alomar, F Galán-Prado, PJ Ballester, ...
IEEE Transactions on Neural Networks and Learning Systems 29 (4), 1371 - 1375, 2018
202018
High-density liquid-state machine circuitry for time-series forecasting
JL Rosselló, ML Alomar, A Morro, A Oliver, V Canals
International journal of neural systems 26 (05), 1550036, 2016
202016
Design hardening of nanometer SRAMs through transistor width modulation and multi-Vt combination
G Torrens, B Alorda, S Barceló, JL Rosselló, SA Bota, J Segura
IEEE Transactions on Circuits and Systems II: Express Briefs 57 (4), 280-284, 2010
202010
Probabilistic-based neural network implementation
JL Rosselló, V Canals, A Morro
The 2012 International Joint Conference on Neural Networks (IJCNN), 1-7, 2012
162012
Power-delay modeling of dynamic CMOS gates for circuit optimization
JL Rosselló, J Segura
IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE …, 2001
162001
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