| Dynamic ‘hour glass’ model for SET and RESET in HfO< inf> 2</inf> RRAM R Degraeve, A Fantini, S Clima, B Govoreanu, L Goux, YY Chen, ... VLSI Technology (VLSIT), 2012 Symposium on, 75-76, 2012 | 104 | 2012 |
| Spin-Hall-assisted magnetic random access memory A Van den Brink, S Cosemans, S Cornelissen, M Manfrini, A Vaysset, ... Applied Physics Letters 104 (1), 012403, 2014 | 76 | 2014 |
| The VO2 interface, the metal-insulator transition tunnel junction, and the metal-insulator transition switch On-Off resistance K Martens, IP Radu, S Mertens, X Shi, L Nyns, S Cosemans, P Favia, ... Journal of Applied Physics 112 (12), 124501, 2012 | 50 | 2012 |
| Time and workload dependent device variability in circuit simulations D Rodopoulos, SB Mahato, VV de Almeida Camargo, B Kaczer, ... 2011 IEEE International Conference on IC Design & Technology, 1-4, 2011 | 50 | 2011 |
| A low-power embedded SRAM for wireless applications S Cosemans, W Dehaene, F Catthoor Solid-State Circuits, IEEE Journal of 42 (7), 1607-1617, 2007 | 50 | 2007 |
| A 3.6 pJ/Access 480 MHz, 128 kb on-chip SRAM with 850 MHz boost mode in 90 nm CMOS with tunable sense amplifiers S Cosemans, W Dehaene, F Catthoor Solid-State Circuits, IEEE Journal of 44 (7), 2065-2077, 2009 | 49 | 2009 |
| Design and benchmarking of hybrid CMOS-spin wave device circuits compared to 10nm CMOS O Zografos, B Sorée, A Vaysset, S Cosemans, L Amaru, PE Gaillardon, ... 2015 IEEE 15th International Conference on Nanotechnology (IEEE-NANO), 686-689, 2015 | 39 | 2015 |
| Analysis of vertical cross-point resistive memory (VRRAM) for 3D RRAM design L Zhang, S Cosemans, DJ Wouters, B Govoreanu, G Groeseneken, ... 2013 5th IEEE International Memory Workshop, 155-158, 2013 | 36 | 2013 |
| High-drive current (>1MA/cm2) and highly nonlinear (>103) TiN/amorphous-Silicon/TiN scalable bidirectional selector with excellent reliability and its variability … L Zhang, B Govoreanu, A Redolfi, D Crotti, H Hody, V Paraschiv, ... 2014 IEEE International Electron Devices Meeting, 6.8. 1-6.8. 4, 2014 | 35 | 2014 |
| One-selector one-resistor cross-point array with threshold switching selector L Zhang, S Cosemans, DJ Wouters, G Groeseneken, M Jurczak, ... IEEE Transactions on Electron Devices 62 (10), 3250-3257, 2015 | 34 | 2015 |
| Hourglass concept for RRAM: a dynamic and statistical device model R Degraeve, A Fantini, N Raghavan, L Goux, S Clima, YY Chen, ... Proceedings of the 21th International Symposium on the Physical and Failure …, 2014 | 34 | 2014 |
| Selector design considerations and requirements for 1 SIR RRAM crossbar array L Zhang, S Cosemans, DJ Wouters, G Groeseneken, M Jurczak, ... 2014 IEEE 6th International Memory Workshop (IMW), 1-4, 2014 | 34 | 2014 |
| A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, ultra low leakage power memory using dynamic cell stability and a dual swing data link B Rooseleer, S Cosemans, W Dehaene ESSCIRC (ESSCIRC), 2011 Proceedings of the, 519-522, 2011 | 32 | 2011 |
| Modular sub-wavelength diffractive light modulator for high-definition holographic displays R Stahl, V Rochus, X Rottenberg, S Cosemans, L Haspeslagh, S Severi, ... Journal of Physics: Conference Series 415 (1), 012057, 2013 | 28 | 2013 |
| A 4.4 pJ/Access 80 MHz, 128 kbit Variability Resilient SRAM With Multi-Sized Sense Amplifier Redundancy V Sharma, S Cosemans, M Ashouei, J Huisken, F Catthoor, W Dehaene Solid-State Circuits, IEEE Journal of, 1-1, 2011 | 26 | 2011 |
| A 3.6 pJ/access 480MHz, 128Kbit on-chip SRAM with 850MHz boost mode in 90nm CMOS with tunable sense amplifiers to cope with variability S Cosemans, W Dehaene, F Catthoor Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European, 278-281, 2008 | 24 | 2008 |
| Quantification of sense amplifier offset voltage degradation due to zero-and run-time variability I Agbo, M Taouil, S Hamdioui, P Weckx, S Cosemans, P Raghavan, ... 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 725-730, 2016 | 22 | 2016 |
| Variability-aware design of low power SRAM memories S Cosemans Katholieke Universiteit Leuven, 2009 | 22 | 2009 |
| On the optimal ON/OFF resistance ratio for resistive switching element in one-selector one-resistor crosspoint arrays L Zhang, S Cosemans, DJ Wouters, G Groeseneken, M Jurczak, ... IEEE Electron Device Letters 36 (6), 570-572, 2015 | 21 | 2015 |
| On-chip optical interconnects versus electrical interconnects for high-performance applications M Stucchi, S Cosemans, J Van Campenhout, Z Tőkei, G Beyer Microelectronic engineering 112, 84-91, 2013 | 20 | 2013 |
Leqi ZhangMentor GraphicsVerified email at mentor.com
Leqi ZhangMentor GraphicsVerified email at mentor.com