| A magnetic tunnel junction based true random number generator with conditional perturb and real-time output probability tracking WH Choi, Y Lv, J Kim, A Deshpande, G Kang, JP Wang, CH Kim 2014 IEEE International Electron Devices Meeting, 12.5. 1-12.5. 4, 2014 | 156 | 2014 |
| A 0.31–1 GHz fast-corrected duty-cycle corrector with successive approximation register for DDR DRAM applications YJ Min, CH Jeong, KY Kim, WH Choi, JP Son, C Kim, SW Kim IEEE transactions on very large scale integration (VLSI) systems 20 (8 …, 2011 | 53 | 2011 |
| Managing refresh operations for a memory device M Qin, WH Choi, Z Bandic US Patent 10,566,048, 2020 | 40 | 2020 |
| Vector-matrix multiplication using non-volatile memory cells WH Choi, M Lueker-boden US Patent 10,528,643, 2020 | 34 | 2020 |
| Configurable precision neural network with differential binary non-volatile memory cell structure WH Choi, PF Chiu, W Ma, M Lueker-boden US Patent 10,643,705, 2020 | 29 | 2020 |
| Spin-Hall effect MRAM based cache memory: A feasibility study J Kim, B Tuohy, C Ma, WH Choi, I Ahmed, D Lilja, CH Kim 2015 73rd Annual Device Research Conference (DRC), 117-118, 2015 | 28 | 2015 |
| Cross-point memory array addressing WH Choi, W Parkinson, Z Bandic, J O'toole, M Lueker-boden US Patent 10,497,438, 2019 | 20 | 2019 |
| A binarized neural network accelerator with differential crosspoint memristor array for energy-efficient MAC operations PF Chiu, WH Choi, W Ma, M Qin, M Lueker-Boden 2019 IEEE international symposium on circuits and systems (ISCAS), 1-5, 2019 | 20 | 2019 |
| High-density 3d vertical reram with bidirectional threshold-type selector WH Choi, J Kumar, D Bedau, ZZ Bandic, SH Song US Patent App. 15/588,422, 2018 | 20 | 2018 |
| Optimization of on-chip switched-capacitor DC-DC converters for high-performance applications P Zhou, WH Choi, B Kim, CH Kim, SS Sapatnekar Proceedings of the International Conference on Computer-Aided Design, 263-270, 2012 | 20 | 2012 |
| Realization of neural networks with ternary inputs and binary weights in NAND memory arrays TT Hoang, WH Choi, M Lueker-boden US Patent 11,170,290, 2021 | 19 | 2021 |
| Differential non-volatile memory cell for artificial neural network PF Chiu, WH Choi, W Ma, M Lueker-boden US Patent 10,643,119, 2020 | 19 | 2020 |
| Content addressable memory with spin-orbit torque devices WH Choi, KIM Jongyeon US Patent 11,152,067, 2021 | 17 | 2021 |
| A test circuit based on a ring oscillator array for statistical characterization of Plasma-Induced Damage WH Choi, S Satapathy, J Keane, CH Kim Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 1-4, 2014 | 16 | 2014 |
| Pipelining to improve neural network inference accuracy W Ma, M Qin, WH Choi, PF Chiu, M Van Lueker-Boden US Patent App. 16/180,462, 2020 | 15 | 2020 |
| An 8-bit analog-to-digital converter based on the voltage-dependent switching probability of a magnetic tunnel junction WH Choi, Y Lv, H Kim, JP Wang, CH Kim 2015 Symposium on VLSI Technology (VLSI Technology), T162-T163, 2015 | 14 | 2015 |
| A physical unclonable function based on capacitor mismatch in a charge-redistribution SAR-ADC Q Tang, WH Choi, L Everson, KK Parhi, CH Kim 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018 | 13 | 2018 |
| Realization of binary neural networks in NAND memory arrays WH Choi, PF Chiu, W Ma, M Qin, GJ Hemink, M Lueker-boden US Patent 11,328,204, 2022 | 12 | 2022 |
| A revolving reference odometer circuit for BTI-induced frequency fluctuation measurements under fast DVFS transients S Satapathy, WH Choi, X Wang, CH Kim 2015 IEEE International Reliability Physics Symposium, 6A. 3.1-6A. 3.5, 2015 | 12 | 2015 |
| An array-based circuit for characterizing latent Plasma-Induced Damage WH Choi, P Jain, CH Kim 2013 IEEE International Reliability Physics Symposium (IRPS), 4A. 3.1-4A. 3.4, 2013 | 12 | 2013 |
