| Power mapping and modeling of multi-core processors K Dev, AN Nowroz, S Reda International Symposium on Low Power Electronics and Design (ISLPED), 39-44, 2013 | 45 | 2013 |
| Distributed memory controller MR Meswani, DA Roberts, Y Eckert, K Dev, J Kalamatianos, I Paul US Patent App. 14/862,011, 2017 | 22 | 2017 |
| Blind identification of thermal models and power sources from thermal measurements S Reda, K Dev, A Belouchrani IEEE Sensors Journal 18 (2), 680-691, 2017 | 20 | 2017 |
| A taxonomy of gpgpu performance scaling A Majumdar, G Wu, K Dev, JL Greathouse, I Paul, W Huang, ... 2015 IEEE International Symposium on Workload Characterization, 118-119, 2015 | 20 | 2015 |
| Scheduling challenges and opportunities in integrated cpu+ gpu processors K Dev, S Reda Proceedings of the 14th ACM/IEEE Symposium on Embedded Systems for Real-Time …, 2016 | 18 | 2016 |
| Workload-aware power gating design and run-time management for massively parallel gpgpus K Dev, S Reda, I Paul, W Huang, W Burleson 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 242-247, 2016 | 12 | 2016 |
| Configuring fast memory as cache for slow memory K Dev, MR Meswani, DA Roberts, E Y, I Paul, J Kalamatianos US Patent US20170083444A1, 2017 | 10 | 2017 |
| Power-aware characterization and mapping of workloads on cpu-gpu processors K Dev, X Zhan, S Reda 2016 IEEE International Symposium on Workload Characterization (IISWC), 1-2, 2016 | 10 | 2016 |
| Power mapping and modeling system for integrated circuits S Reda, A Nowroz, K Dev US Patent 10,175,705, 2019 | 8 | 2019 |
| High-throughput TSV testing and characterization for 3D integration using thermal mapping K Dev, G Woods, S Reda Proceedings of the 50th Annual Design Automation Conference, 1-6, 2013 | 8 | 2013 |
| A framework for evaluating promising power efficiency techniques in future GPUs for HPC K Dev, I Paul, W Huang Proceedings of the 24th High Performance Computing Symposium, 1-8, 2016 | 5 | 2016 |
| Implications of integrated cpu-gpu processors on thermal and power management techniques K Dev, I Paul, W Huang, Y Eckert, W Burleson, S Reda arXiv preprint arXiv:1808.09651, 2018 | 4 | 2018 |
| Design of a scalable DNA shearing system using phased-array ultrasonic transducer K Dev, S Sharma, V Vivek, B Hadimioglu, Y Massoud 2011 18th IEEE International Conference on Electronics, Circuits, and …, 2011 | 4 | 2011 |
| Analytical modeling and design of ring shaped piezoelectric transducers K Dev, V Vivek, B Hadimioglu, Y Massoud 2011 18th IEEE International Conference on Electronics, Circuits, and …, 2011 | 4 | 2011 |
| Scheduling on cpu+ gpu processors under dynamic conditions K Dev, X Zhan, S Reda Journal of Low Power Electronics 13 (4), 551-568, 2017 | 3 | 2017 |
| Apparatus and method for using ultrasonic radiation for controlled fragmentation of chains of nucleic acids V Vivek, B Hadimioglu, S Sharma, DEV Kapil | 3 | 2017 |
| Analytical Modeling and Design of Fresnel Lens Transducers K Dev, V Vivek, B Hadimioglu, Y Massoud arXiv preprint arXiv:1907.09339, 2019 | 2 | 2019 |
| Design of a Fast, Efficient and Controlled DNA Shearing System Based on Lateral Acoustic Waves K Dev Rice University, 2011 | 2 | 2011 |
| New techniques for power-efficient cpu-gpu processors K Dev Brown University PROVIDENCE, RHODE ISLAND, 2017 | 1 | 2017 |
| On the design of balanced carbon nanotube field-effect transistor gates K Dev, Y Massoud 2011 18th IEEE International Conference on Electronics, Circuits, and …, 2011 | | 2011 |
Sherief RedaProfessor, Brown University | Amazon ScholarVerified email at brown.edu
