A 39-GHz Frequency Tripler With> 40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS M Bassi, G Boi, F Padovan, J Fritzin, S Di Martino, D Knauder, ... ESSCIRC 2019-IEEE 45th European Solid State Circuits Conference (ESSCIRC …, 2019 | 22 | 2019 |
A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise L Tomasin, P Andreani, G Boi, F Padovan, A Bevilacqua IEEE Journal of Solid-State Circuits 57 (9), 2802-2811, 2022 | 15 | 2022 |
A 10.7–14.1 GHz Reconfigurable Octacore DCO with− 126 dBc/Hz Phase Noise at 1 MHz offset in 28 nm CMOS L Tomasin, G Boi, F Padovan, A Bevilacqua 2021 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 179-182, 2021 | 13 | 2021 |
Digital phase-locked loop with a dynamic element matching circuit and a digitally controlled oscillator L Grimaldi, G Boi, D Cherniak, F Padovan US Patent 11,184,013, 2021 | 4 | 2021 |
Calibrating an injection locked oscillator M Bassi, G Boi, D Cherniak, F Padovan US Patent 10,855,296, 2020 | 3 | 2020 |
Oscillator with inductor and programmable capacitor bank F Padovan, M Bassi, G Boi, D Cherniak, L Grimaldi US Patent 11,196,382, 2021 | 1 | 2021 |
Digital coarse locking in digital phase-locked loops L Grimaldi, T Bauernfeind, D Cherniak, F Versolatto, A Wightwick, ... US Patent 11,909,405, 2024 | | 2024 |
Peak detector calibration M Bassi, G Boi, D Cherniak, F Padovan US Patent 11,079,415, 2021 | | 2021 |