| MERS: statistical test generation for side-channel analysis based Trojan detection Y Huang, S Bhunia, P Mishra Proceedings of the 2016 ACM SIGSAC Conference on Computer and Communications …, 2016 | 124 | 2016 |
| Scalable test generation for Trojan detection using side channel analysis Y Huang, S Bhunia, P Mishra IEEE Transactions on Information Forensics and Security 13 (11), 2746-2760, 2018 | 112 | 2018 |
| An automated configurable Trojan insertion framework for dynamic trust benchmarks J Cruz, Y Huang, P Mishra, S Bhunia 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018 | 82 | 2018 |
| System-on-chip security F Farahmandi, Y Huang, P Mishra Springer, 2020 | 71 | 2020 |
| Trojan localization using symbolic algebra F Farahmandi, Y Huang, P Mishra 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 591-597, 2017 | 69 | 2017 |
| Trace buffer attack: Security versus observability study in post-silicon debug Y Huang, A Chattopadhyay, P Mishra 2015 IFIP/IEEE International Conference on Very Large Scale Integration …, 2015 | 20 | 2015 |
| Cache reconfiguration using machine learning for vulnerability-aware energy optimization A Ahmed, Y Huang, P Mishra ACM Transactions on Embedded Computing Systems (TECS) 18 (2), 1-24, 2019 | 19 | 2019 |
| Reliability and energy-aware cache reconfiguration for embedded systems Y Huang, P Mishra 2016 17th International Symposium on Quality Electronic Design (ISQED), 313-318, 2016 | 17 | 2016 |
| Vulnerability-aware energy optimization for reconfigurable caches in multitasking systems Y Huang, P Mishra IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 16 | 2018 |
| Trace buffer attack on the AES cipher Y Huang, P Mishra Journal of Hardware and Systems Security 1, 68-84, 2017 | 16 | 2017 |
| Automated test generation for detection of malicious functionality F Farahmandi, Y Huang, P Mishra, F Farahmandi, Y Huang, P Mishra System-on-Chip Security: Validation and Verification, 153-171, 2020 | 10 | 2020 |
| Vulnerability-aware energy optimization using reconfigurable caches in multicore systems Y Huang, P Mishra 2017 IEEE International Conference on Computer Design (ICCD), 241-248, 2017 | 9 | 2017 |
| SoC security verification using property checking F Farahmandi, Y Huang, P Mishra, F Farahmandi, Y Huang, P Mishra System-on-Chip Security: Validation and Verification, 137-152, 2020 | 6 | 2020 |
| Formal approaches to hardware trust verification F Farahmandi, Y Huang, P Mishra The Hardware Trojan War: Attacks, Myths, and Defenses, 183-202, 2018 | 6 | 2018 |
| Trojan detection using machine learning F Farahmandi, Y Huang, P Mishra, F Farahmandi, Y Huang, P Mishra System-on-Chip Security: Validation and Verification, 173-188, 2020 | 5 | 2020 |
| Hardware trojan detection schemes using path delay and side-channel analysis F Farahmandi, Y Huang, P Mishra, F Farahmandi, Y Huang, P Mishra System-on-Chip Security: Validation and Verification, 221-271, 2020 | 4 | 2020 |
| Vulnerability-aware dynamic reconfiguration of partially protected caches Y Huang, P Mishra 2020 21st International Symposium on Quality Electronic Design (ISQED), 255-260, 2020 | 3 | 2020 |
| Test generation for detection of malicious parametric variations Y Huang, P Mishra Hardware IP Security and Trust, 325-340, 2017 | 3 | 2017 |
| The future of security validation and verification F Farahmandi, Y Huang, P Mishra, F Farahmandi, Y Huang, P Mishra System-on-Chip Security: Validation and Verification, 273-279, 2020 | 2 | 2020 |
| SoC trust metrics and benchmarks F Farahmandi, Y Huang, P Mishra, F Farahmandi, Y Huang, P Mishra System-on-Chip Security: Validation and Verification, 37-57, 2020 | 2 | 2020 |
Prabhat MishraProfessor, Univ. of Florida, IEEE Fellow, AAAS Fellow, ACM Distinguished MemberVerified email at ufl.edu
