Omer Khan
TitleCited byYear
Suppressing the oblivious ram timing channel while making information leakage and program efficiency trade-offs
CW Fletcher, L Ren, X Yu, M Van Dijk, O Khan, S Devadas
High Performance Computer Architecture (HPCA), 2014 IEEE 20th International …, 2014
802014
Crono: A benchmark suite for multithreaded graph algorithms executing on futuristic multicores
M Ahmad, F Hijaz, Q Shi, O Khan
2015 IEEE International Symposium on Workload Characterization, 44-55, 2015
742015
Scalable, accurate multicore simulation in the 1000-core era
M Lis, P Ren, MH Cho, KS Shim, CW Fletcher, O Khan, S Devadas
(IEEE ISPASS) IEEE International Symposium on Performance Analysis of …, 2011
702011
Hornet: A cycle-level multicore simulator
P Ren, M Lis, MH Cho, KS Shim, CW Fletcher, O Khan, N Zheng, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012
652012
DARSIM: a parallel cycle-level NoC simulator
M Lis, KS Shim, MH Cho, P Ren, O Khan, S Devadas
632010
DARSIM: a parallel cycle-level NoC simulator
M Lis, KS Shim, MH Cho, P Ren, O Khan, S Devadas
632010
A self-adaptive system architecture to address transistor aging
O Khan, S Kundu
2009 Design, Automation & Test in Europe Conference & Exhibition, 81-86, 2009
582009
Performance per watt benefits of dynamic core morphing in asymmetric multicores
R Rodrigues, A Annamalai, I Koren, S Kundu, O Khan
2011 International Conference on Parallel Architectures and Compilation …, 2011
482011
The locality-aware adaptive cache coherence protocol
G Kurian, O Khan, S Devadas
ACM SIGARCH Computer Architecture News 41 (3), 523-534, 2013
432013
Thread relocation: A runtime architecture for tolerating hard errors in chip multiprocessors
O Khan, S Kundu
IEEE Transactions on Computers 59 (5), 651-665, 2010
272010
Thread relocation: A runtime architecture for tolerating hard errors in chip multiprocessors
O Khan, S Kundu
IEEE Transactions on Computers 59 (5), 651-665, 2010
272010
Thread migration prediction for distributed shared caches
KS Shim, M Lis, O Khan, S Devadas
IEEE Computer Architecture Letters 13 (1), 53-56, 2012
26*2012
Deadlock-free fine-grained thread migration
MH Cho, KS Shim, M Lis, O Khan, S Devadas
Proceedings of the Fifth ACM/IEEE International Symposium, 33-40, 2011
262011
A self-adaptive scheduler for asymmetric multi-cores
O Khan, S Kundu
Proceedings of the 20th symposium on Great lakes symposium on VLSI, 397-400, 2010
262010
Execution migration
S Devadas, O Khan, M Lis, KS Shim, MH Cho
US Patent 8,904,154, 2014
252014
Advancing the state-of-the-art in hardware trojans detection
SK Haider, C Jin, M Ahmad, DM Shila, O Khan, M van Dijk
IEEE Transactions on Dependable and Secure Computing 16 (1), 18-32, 2017
242017
Advancing the state-of-the-art in hardware trojans detection
SK Haider, C Jin, M Ahmad, DM Shila, O Khan, M van Dijk
IEEE Transactions on Dependable and Secure Computing 16 (1), 18-32, 2017
242017
Locality-aware data replication in the last-level cache
G Kurian, S Devadas, O Khan
2014 IEEE 20th International Symposium on High Performance Computer …, 2014
242014
Improving yield and reliability of chip multiprocessors
A Pan, O Khan, S Kundu
Proceedings of the Conference on Design, Automation and Test in Europe, 490-495, 2009
222009
Memory coherence in the age of multicores
M Lis, KS Shim, MH Cho, S Devadas
2011 IEEE 29th International Conference on Computer Design (ICCD), 1-8, 2011
212011
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