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Josue V. Quiroga
Josue V. Quiroga
Research Engineer
Verified email at bsc.es
Title
Cited by
Cited by
Year
Disaggregated computing. an evaluation of current trends for datacentres
H Meyer, JC Sancho, JV Quiroga, F Zyulkyarov, D Roca, M Nemirovsky
Procedia Computer Science 108, 685-694, 2017
302017
Fog function virtualization: A flexible solution for iot applications
D Roca, JV Quiroga, M Valero, M Nemirovsky
2017 Second International Conference on Fog and Mobile Edge Computing (FMEC …, 2017
282017
Vitruvius+: an area-efficient RISC-V decoupled vector coprocessor for high performance computing applications
F Minervini, O Palomar, O Unsal, E Reggiani, J Quiroga, J Marimon, ...
ACM Transactions on Architecture and Code Optimization 20 (2), 1-25, 2023
222023
Evaluation of a rack-scale disaggregated memory prototype for cloud data centers
JV Quiroga, M Torrents, N Sonmez, D Theodoropoulos, F Zyulkyarov, ...
Proceedings of the 30th International Workshop on Rapid System Prototyping …, 2019
52019
Heterogeneous CPU/GPU Memory Hierarchy Analysis and Optimization
JV Quiroga Esparza
Universitat Politècnica de Catalunya. Facultat d'Informàtica de Barcelona …, 2015
32015
Reusable Verification Environment for a RISC-V Vector Accelerator
J Quiroga, RI Genovese, I Díaz, H Yano, A Ali, N Sommez, ...
Design and Verification Conference & Exhibition Europe (DVCon Europe) 2022 …, 2023
12023
Functional Verification of a RISC-V Vector Accelerator
V Jimenez, M Rodriguez, M Dominguez, J Sans, I Diaz, L Valente, ...
IEEE Design & Test 40 (3), 36-44, 2022
12022
METODOLOGÍA PARA LA DETECCIÓN DE RIESGOS DE DATOS APLICADA A UN PROCESADOR RISC-V DE 5 ETAPAS (DATAHAZARD DETECTION METODOLIGY FOR A RISC-V 5 STAGE PIPELINE PROCESOR)
EAM Ruiz, JVQ Esparza, MAG Navarro
Pistas Educativas 44 (144), 2023
2023
DISEÑO DE PROCESADOR RISC-V DE 32-BITS DE CICLO ÚNICO (DESIGN OF A SINGLE-CYCLE 32-BIT RISC-V PROCESSOR)
MAG Navarro, JVQ Esparza, ÁEA Huerta, CAB Barragán, IRP Cantoya, ...
Pistas Educativas 44 (143), 2022
2022
Resource utilization analysis in a disaggregated datacenter architecture
M Torrents, J Quiroga, T Arkose, F Zyulkyarov, M Nemirovsky
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