Feasibility of imaging photoplethysmography J Zheng, S Hu, V Chouliaras, R Summers
2008 International Conference on BioMedical Engineering and Informatics 2, 72-75, 2008
131 2008 Study of the effects of SEU-induced faults on a pipeline protected microprocessor E Touloupis, JA Flint, VA Chouliaras, DD Ward
IEEE Transactions on Computers 56 (12), 1585-1596, 2007
70 2007 Hardware assisted rate distortion optimization with embedded CABAC accelerator for the H. 264 advanced video codec YL Nunez-Yanez, VA Chouliaras, D Alfonso, FS Rovati
IEEE Transactions on Consumer Electronics 52 (2), 590-597, 2006
51 2006 Remote simultaneous dual wavelength imaging photoplethysmography: a further step towards 3-D mapping of skin blood microcirculation J Zheng, S Hu, V Azorin-Peris, A Echiadis, V Chouliaras, R Summers
Multimodal Biomedical Imaging III 6850, 153-160, 2008
47 2008 Thread-parallel MPEG-2, MPEG-4 and H. 264 video encoders for SoC multi-processor architectures TR Jacobs, VA Chouliaras, DJ Mulvaney
IEEE Transactions on Consumer Electronics 52 (1), 269-275, 2006
41 2006 An efficient multiple precision floating-point multiplier K Manolopoulos, D Reisis, VA Chouliaras
2011 18th IEEE International Conference on Electronics, Circuits, and …, 2011
34 2011 Hardware implementation of a novel genetic algorithm Z Zhu, DJ Mulvaney, VA Chouliaras
Neurocomputing 71 (1-3), 95-106, 2007
33 2007 An efficient multiple precision floating-point multiply-add fused unit K Manolopoulos, D Reisis, VA Chouliaras
Microelectronics journal 49, 10-18, 2016
32 2016 High-performance arithmetic coding VLSI macro for the H264 video compression standard JL Nunez, VA Chouliaras
IEEE Transactions on Consumer Electronics 51 (1), 144-151, 2005
31 2005 A configurable and programmable motion estimation processor for the H. 264 video codec JL Nunez-Yanez, E Hung, V Chouliaras
2008 International Conference on Field Programmable Logic and Applications …, 2008
29 2008 A Novel X Wu, VA Chouliaras, JL Nunez-Yanez, RM Goodall
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16 (3), 217-228, 2008
26 2008 An efficient dual-mode floating-point multiply-add fused unit K Manolopoulos, D Reisis, VA Chouliaras
2010 17th IEEE International Conference on Electronics, Circuits and Systems …, 2010
24 2010 Dynamic voltage scaling in a FPGA-based system-on-chip JL Nunez-Yanez, V Chouliaras, J Gaisler
2007 International Conference on Field Programmable Logic and Applications …, 2007
24 2007 A multi-standard video accelerator based on a vector architecture VA Chouliaras, JL Nunez, DJ Mulvaney, FS Rovati, D Alfonso
IEEE Transactions on Consumer Electronics 51 (1), 160-167, 2005
22 2005 A configurable statistical lossless compression core based on variable order Markov modeling and arithmetic coding JL Nunez-Yanez, VA Chouliaras
IEEE Transactions on Computers 54 (11), 1345-1359, 2005
21 2005 A remote approach to measure blood perfusion from the human face J Zheng, S Hu, AS Echiadis, V Azorin-Peris, P Shi, V Chouliaras
Advanced Biomedical and Clinical Diagnostic Systems VII 7169, 221-227, 2009
20 2009 A novel genetic algorithm designed for hardware implementation Z Zhu, D Mulvaney, V Chouliaras
International Journal of Electrical and Computer Engineering 1 (12), 1842-1849, 2007
18 2007 Design and implementation of a high-performance and silicon efficient arithmetic coding accelerator for the H. 264 advanced video codec JL Núñez-Yáñez, VA Chouliaras
2005 IEEE International Conference on Application-Specific Systems …, 2005
17 2005 Scalar coprocessors for accelerating the G723. 1 and G729A speech coders VA Chouliaras, J Nunez
IEEE Transactions on Consumer Electronics 49 (3), 703-710, 2003
17 2003 A high performance VLSI FFT architecture K Babionitakis, K Manolopoulos, K Nakos, D Reisis, N Vlassopoulos, ...
2006 13th IEEE International Conference on Electronics, Circuits and Systems …, 2006
16 2006 
